lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<rjo> pong
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* sb0 is back in hk
<kristianpaul> :oh:
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<rjo> sb0: bumpy flight? ;)
<sb0> no, it went smoothly though headwinds made it slow (over 15 hours)
<kristianpaul> Where are you going at hk?
<sb0> I live there now
<kristianpaul> oh, k
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<GitHub39> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/Eaaopg
<GitHub39> migen/master 4542de2 Sebastien Bourdeauducq: genlib/fsm: add NextValue to replace reg/reg_next/ce pattern
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<GitHub137> [artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/Xp7TtQ
<GitHub137> artiq/master 744e784 Yann Sionneau: devices: initial LDA controller
<GitHub137> artiq/master 57e25c7 Sebastien Bourdeauducq: lda: minor fixes and refactoring
<GitHub78> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/ZwP-oQ
<GitHub78> artiq/master dc27c2e Sebastien Bourdeauducq: lda: remove excessive verbosity
<GitHub175> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/SzsNVg
<GitHub175> artiq/master f12389c Sebastien Bourdeauducq: doc/manual: add controller default TCP port list
<_florent_> hi
<_florent_> I just found why the ressource usage of the LSU was abnormal on the KC705 port with Vivado (for LM32 and mor1kx):
<_florent_> 1) It's not the LSU but the L2 cache --> first Vivado bug in the hierachical report...
<_florent_> 2) Vivado is not able to recognize this as a memory: http://pastebin.com/p7QK4JCa
<_florent_> to do a quick test, I've used FullMemoryWE on the wishbone2lasmi bridge, it's OK
<_florent_> but we will have to split manually memories in 32bits memories for now with Vivado --> second Vivado bug
<_florent_> I contacted a FAE and it should be fixed in the next Vivado releases.
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<sb0> _florent_, cool
<_florent_> now generating MiniSoC on KC705 takes less than 5 minutes :)
<kristianpaul> wow
<kristianpaul> Using migen?
<_florent_> yes :)
<sb0> _florent_, with FullMemoryWE on wishbone2lasmi?
<sb0> or did you get a modified vivado from xilinx?
<_florent_> yes by using FullMemoryWE, but it's not optimal
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<kristianpaul> so vivado is faster than ise for the spartan 6?
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