05:20 <sb0> http://randombytes.net/

11:24 <sb0> ysionneau, what is the POST-WRITE state for?

11:26 <ysionneau> I introduced it to try to fix the "DDR" case on M1 but it didn't help in the end ... I should remove it and resend the patch I guess

11:26 <ysionneau> I wanted to make sure I correctly resetted the cs_n and wrdata_en rddata_en

11:26 <sb0> let me just remove it

11:27 <ysionneau> and also the ack

11:27 <sb0> also, cs_n can be tied to 0 iirc

11:27 <ysionneau> but if it's done correctly in the IDLE state it should be ok

11:27 <sb0> it's even likely that the toggling of cs_n messes up the write on the ddr

11:28 <ysionneau> cs_n can stay low but then for NOPs I need to put RAS_N/CAS_N/WE_N to H

11:28 <sb0> yes

11:28 <ysionneau> by just touching cs_n I can do NOPs

11:28 <ysionneau> instead of toggling the others signals

11:28 <ysionneau> but yes I can give this a try to see if it's the origin of the issue

11:28 <sb0> well you need to control ras/cas/we anyway

11:28 <sb0> no need to touch cs

11:29 <sb0> cs is only useful when you have several dram chips in parallel

11:29 <ysionneau> I mean, when I want to go from a READ cmd to a NOP, I can just do cs_n.eq(1) and I have a NOP

11:29 <ysionneau> if I leave cs_n to 0 then I need to switch the other wires to 1

11:29 <sb0> by setting the reset value of ras_n/cas_n/we_n to 1, you have a nop whenever you don't touch them in the fsm

11:29 <ysionneau> ah right

11:30 <ysionneau> ok will try that this afternoon

11:30 <sb0> also remember that fsm.act() statements are combinatorial

11:30 <ysionneau> yes I discovered that, I thought at first that it was synchronous to the clock edge

11:30 <sb0> so there's no "resetting" of some value you set in the previous state

11:31 <sb0> "dfi.phases[rdphase].rddata_en.eq(1), dfi.phases[rdphase].wrdata_en.eq(1)," in the same state is obviously incorrect

11:32 <ysionneau> I think I got this from simulating lasmicon but I can verify

11:32 <ysionneau> at first indeed I was only doing the rddata_en (for the READ state)

11:32 <ysionneau> I can recheck that

11:33 <sb0> "Cat([phase.wrdata_mask for phase in dfi.phases]).eq(~bus.sel)" can probably go outside the fsm

11:33 <ysionneau> I have to go, be back after lunch!

11:33 <sb0> generally, use the reset value of signals and don't needlessly drive them in the fsm

11:34 <sb0> stuff like "row_open.eq(0)," in IDLE is just clutter

11:35 <sb0> <ysionneau> I wanted to make sure I correctly resetted the cs_n and wrdata_en rddata_en <ysionneau> and also the ack <<< as I said, fsm.act() is combinatorial so there's no need for thart

11:37 <GitHub60> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/ZUcxAA

11:37 <GitHub60> migen/master ee928a8 Yann Sionneau: Wishbone DownConverter: Fix sel signal

11:42 <sb0> does the refresh work? I never intended a state to be both in act() and the entry state (first parameter) of delayed_enter()

11:45 <sb0> the comment "# We let A10 be 0 to disable row Auto-Precharge" is misplaced

11:48 <sb0> "If(~wb_access, NextState("IDLE")," in IDLE is also clutter

11:49 <sb0> ah, well, no. it's just confusing. better have If(wb_access, ...) containing the above statements

11:50 <sb0> If(refresh_req, NextState("PRECHARGEALL")).Elif(wb_access, If(hit & bus.we, ...), ...)

14:13 <ysionneau> 12:34 < sb0> generally, use the reset value of signals and don't needlessly drive them in the fsm < ok I see

14:18 <ysionneau> 12:42 < sb0> does the refresh work? < works in simulation and I don't see problem on ARTIQ with the controller, maybe I should do lots of uncached reads from the BIOS to make sure

14:32 <sb0> seems delayed_enter happen to work even if you use act on the same state if delay != 0

14:32 <sb0> but you should still change it

15:07 <ysionneau> humm by reading the generated code it seems the refresh should not work

15:08 <ysionneau> it goes from prechargeall to idle, instead of going from prechargeall to refresh

15:11 <ysionneau> oh, my prechargeall is wrong

15:11 <ysionneau> god it's wrong

15:11 <ysionneau> how did this happen to even work

15:20 <ysionneau> ah no, the ras/cas/we was not in the same order so I misinterpreted the command, it was correct

15:22 <sb0> rjo, have you considered using those transistors designed to drive CRT electron guns? e.g. http://www.nteinc.com/specs/2500to2599/pdf/nte2501.pdf

15:23 <ysionneau> ok so refresh is supposed to work

15:23 <sb0> they take 300V, have high current capability, and should still have some gain at 50MHz

15:27 <sb0> can dissipate 7W with good heatsinking

15:38 <sb0> http://www.nteinc.com/specs/2500to2599/pdf/nte2508.pdf and http://www.nteinc.com/specs/2500to2599/pdf/nte2511.pdf have even better specs

15:39 <sb0> the last one should definitely work

15:40 <sb0> http://www.ntepartsdirect.com/ENG/PRODUCT/NTE2511

15:40 <sb0> http://www.ntepartsdirect.com/ENG/PRODUCT/NTE2512

15:41 <sb0> it's even dirt cheap

15:57 <sb0> ysionneau, change it so you're not using the same state in act() and delayed_enter()

16:01 <ysionneau> in the prechargeall state I do NextState("PRE-REFRESH") and then a delayed_enter("PRE-REFRESH", "REFRESH"...)?

16:08 <sb0> yes

16:20 <sb0> well, nte2508. 2511 doesn't have enough breakdown voltage.

17:10 <ysionneau> hum I forgot to git add sdram/__init__.py