04:36 <whitequark> sb0: ping?

04:36 <whitequark> https://github.com/m-labs/artiq/issues/219#issuecomment-169922910

04:43 <sb0> whitequark, I don't know. 20MB?

04:43 <sb0> rjo, ^

04:51 <whitequark> ok

04:53 <whitequark> sb0: lwip is linked even into the pipistrello runtime, is it?

05:03 <sb0> it should... and eventually the pipistrello should use ppp too

05:04 <sb0> felix_, how is that going by the way?

05:24 <whitequark> sb0: I'm concerned about using lwip's memory pools

05:36 <mithro> sb0: I have a couple more CSR questions

05:36 <mithro> sb0: Why is there a "CSR" class which the other CSRStorage and CSRStatus don't inherit from?

05:37 <mithro> sb0: It seems like that class is instantiated in do_finalize of both those classes

05:37 <mithro> sb0: but I don't quite understand *why* it is doing this?

05:38 <mithro> sb0: Nor why "_CompoundCSR" exists...

05:40 <mithro> sb0: I was trying to create a "clear on read" interrupt style CSR - which I think you suggested I use the self.r signal with, but that only appears on the CSR class not the other ones

05:48 <mithro> sb0: then I got confused

05:49 <sb0> mithro, CSR can be mapped at only one addresses. the CompoundCSRs can be broken down automatically if they exceed the bus data width

05:50 <mithro> sb0: oh

05:53 <sb0> whitequark, why?

05:53 <whitequark> sb0: they require tapping into barely-documented lwip guts

05:58 <mithro> sb0: So, how would someone do the clear on read type system, just a manual instantiation of CSR class and doing the clear on the .r signal?

05:58 <mithro> brb

05:59 <sb0> mithro, you cannot detect reads

06:01 <sb0> whitequark, for what exactly?

06:01 <whitequark> sb0: creating a memory pool.

06:01 <sb0> is that a complicated thing to do?

06:01 <whitequark> I'm currently reading how it's done... you give lwip a file it includes several times deep in its guts, then you have to use its memp_function...

06:01 <whitequark> yes, yes it is

06:01 <whitequark> I'm still not sure how exactly it functions

06:02 <whitequark> I *think* I can implement it now

06:02 <sb0> if lwip is messy (it often is...) are there alternative and nice mallocs?

06:03 <whitequark> I am looking for those right now.

06:03 <whitequark> hell, I wrote a bunch, but I'm not sure if the (well-tested) code I wrote back then is still up somewhere.

07:15 <cr1901_modern> sb0: You need a freestanding malloc()?

07:15 <whitequark> I do

07:16 <cr1901_modern> https://bitbucket.org/trap15/openmem is one that I was planning to use for a ucon (but never did)

07:16 <whitequark> ah I know the author

07:17 <cr1901_modern> Yea, he's a good guy, even if he's not too thrilled with me lately lol

07:19 <cr1901_modern> In any case, you'll need to write the malloc() wrapper yourself, but the hard part should be done for you

07:40 <sb0> cr1901_modern, how is the scan widget coming along?

11:34 <GitHub64> [artiq] sbourdeauducq pushed 1 new commit to applets: http://git.io/vu78R

11:34 <GitHub64> artiq/applets 2199ead Sebastien Bourdeauducq: gui/applets: save/restore state

15:35 <whitequark> ok, there were no better contenders, so I will use trap15's code

17:15 <felix_> i removed everything except lwip from the runtime and still got only a little less than 50% unanswerded pings when doing a flood ping with 1000 bytes payload. with 100 bytes payload only very few packets get lost

17:16 <felix_> i'm currently porting the lwip part of the runtime to a arm cortex m4, to get better debugging capabilities

17:16 <felix_> seems to be some buffer or locking problem

17:18 <felix_> i added some gpio module to the design and connected a logic analyzer to them to have a lok at the interrupt timing, but there should be enough time for the network stack to process the packets

17:20 <felix_> the irq service routine took a bit longer than i expected though

17:32 <felix_> hmm, in this test run, i only got about 30% packet loss