07:36 <rjo> hartytp: but the gateware PI controller and the double buffered thing already achieves that. QSPI does not make it worse.

07:39 <rjo> hartytp: That Urukul QSPI is not non-standard: it will work fine in half-duplex. And there is no QSPI standard anyway.

07:44 <hartytp> rjo: to keep the Kasli ecosystem manageable, I'd like to try to keep this kind of design as general purpose as possible so that we have a few simple reusable designs, rather than a large number of boards that are heavily optimised for individual purposes.

07:45 <hartytp> Maybe that's unavoidable in this case, given our requirements

07:46 <hartytp> But, e.g., if we had a DIP switch and some gates to allow users to switch between "compact" (IDC + standard Kasli gateware) and "high-bandwidth" (4 IDCs and custom gateware)

07:47 <hartytp> then we can use Urukul for our servo. But, it's still a nice general purpose simple RF source for OptiClock and other general lab applications

07:47 <hartytp> but, maybe that's asking for too much from a single design?

07:49 <hartytp> Same for Novogorny: it'd be nice to have the option of running it in high-bandwidth mode for our custom servo, but still allow users to run it from the "standard" Kasli gateware if they want a slower more generic board

09:38 <hartytp> NB obvious mistakes in IDC count in previous post: both "compact" and "high-bandwidth" cases use 2 IDCs as on Wiki. If we can support both methods (DIP switch to select?) then I think all my concerns would be met

10:40 <rjo> interestingly, AD seems to use the same technique to get high DDS data rates that we use. maybe more surprisingly they appear to need interleaving already for >300 MHz data rate even though it's hard silicon.

11:17 <rjo> hartytp: i misremembered my old reading of the AD9912 datasheet. it doesn't have an ASF but a DAC full-scale current (FSC) register. "8.6 mA to 31.7 mA with 10 bit granularity".

11:21 <larsc> what's that technique? Interleaving multiple DDS with a phase offset?

11:28 <rjo> larsc: yes. mostly trivial. it only gets a bit complicated if you want to ramp frequencies and or phases and the proper updates require a bit of thinking.

11:48 <rjo> but what is the challenge with a DDS core that has >300 MHz logic clock. wide adders?