00:28 <GitHub134> [artiq] jbqubit reopened issue #807: sawg full-scale noise after halting demo_2tone https://github.com/m-labs/artiq/issues/807

05:47 <sb0> In some countries, a no-show charge may also be collected. Please cancel your reservations if you do not intend to fly.

05:47 <sb0> amazing

05:47 <sb0> I thought airlines rules of acquisition couldn't get any shittier

05:48 <whitequark> that's in addition to the cost of the ticket?

05:48 <sb0> it seems so, yes

05:48 <whitequark> and they do it simultaneously with overselling? wow, the nerve of it

05:52 <sb0> I'm wondering what credit card issuer has the easiest chargebacks

05:53 <sb0> e.g. things like https://www.neat.hk/

05:53 <sb0> that would properly deal with this kind of airline bullshit

05:56 <sb0> and yes, from the same document: "5. Cathay Pacific and most major airlines may overbook services. While Cathay Pacific makes every effort to provide seats for confirmed reservations made, we cannot guarantee seat availability."

05:57 <whitequark> "the beatings will continue while customers give us cash"

05:57 <whitequark> sometimes literally

06:03 <sb0> oh and when you cancel, some airlines (idk if cathay does that) charge you money for it. then they give you some credit in travel vouchers that expire after a year

06:03 <sb0> that's their idea of "refundable" tickets

06:04 <sb0> the vouchers, of course, can only be used to book flights on that airline

06:24 <cr1901_modern> sb0: It's prob quicker to ask you, so... in the elapsed() function in time.h in misoc, are you supposed to initialize last_event using timer0_value_read()?

06:25 <cr1901_modern> Actually wait nevermind, I think you're supposed to initialize with period < 0

15:20 <_florent_> sb0, rjo: the boards are back yes

16:47 <sb0> _florent_, good

16:48 <sb0> can you sort out the DAC clocking? we'd like to go as far as possible for the demo next week

16:49 <sb0> rjo, what are the frequencies that should be programmed?

16:50 <sb0> rjo, do you have openocd scripts for sayma?

16:54 <sb0> "Xilinx Virtex-II Series7 bitstream loading"

17:30 <GitHub105> [artiq] sbourdeauducq commented on issue #800: Cannot get it to work with the RTM disconnected:... https://github.com/m-labs/artiq/issues/800#issuecomment-322843230

17:32 <GitHub21> [artiq] sbourdeauducq commented on issue #800: Well. Strangely enough I cannot reproduce the issue after disconnecting the RTM again... https://github.com/m-labs/artiq/issues/800#issuecomment-322843935

17:58 <rjo> sb0: 600 MHz DAC sample clock, 150 MHz RTIO coarse. the other freqs are then implied.

17:59 <rjo> _florent_: greg and joe are debugging the clocking issue as well. or did you make progress on that aready? did they talk to you?

18:34 <sb0> _florent_, why does RGMII require a DCM?

18:35 <sb0> and why are you using, in the same file, sometimes Instance("ODDR2",...) and sometimes DDROutput()

19:36 <sb0> _florent_, generally the DDRInput/DDROutput stuff that you introduced is generally used and implemented very inconsistently.

20:25 <sb0> _florent_, why is DDRInput never implemented?

20:29 <rjo> sb0: if you implement it, c.f. the one from nu-servo

20:31 <sb0> why is it in nu-servo and not in migen? let me move it ...

20:35 <sb0> ok you should be able to remove the nu-servo implementation now

20:35 <GitHub22> [migen] sbourdeauducq pushed 3 new commits to master: https://git.io/v7AIw

20:35 <GitHub22> migen/master d8860cd Sebastien Bourdeauducq: xilinx: add 7-series DDR input

20:35 <GitHub22> migen/master 6169265 Sebastien Bourdeauducq: xilinx: move Spartan-6 DDR output out of generic Xilinx special overrides

20:35 <GitHub22> migen/master 970428e Sebastien Bourdeauducq: xilinx: add Kintex Ultrascale DDR buffers

20:38 <bb-m-labs> build #166 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/166

20:40 <rjo> sb0: sure. it's in nu-servo because i never verified it and the harness for nu-servo is ad-hoc.

20:42 <GitHub146> [nu-servo] jordens pushed 1 new commit to master: https://github.com/m-labs/nu-servo/commit/1814ba6691bd21aea9d393155a2d7e9ee257339c

20:42 <GitHub146> nu-servo/master 1814ba6 Robert Jordens: arty: DDRInput* moved to migen

20:47 <GitHub155> [misoc] sbourdeauducq pushed 2 new commits to master: https://git.io/v7AtO

20:47 <GitHub155> misoc/master 47637ed Sebastien Bourdeauducq: liteeth: remove ad-hoc clk_freq parameter

20:47 <GitHub155> misoc/master 514da94 Sebastien Bourdeauducq: kc705: remove unused default_platform string

20:48 <bb-m-labs> build #229 of misoc is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/229 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>

20:50 <sb0> Can't build /var/lib/buildbot/slaves/debian-stretch-amd64-1/misoc/build/conda/misoc due to environment creation error:

20:50 <sb0> CondaFileNotFoundError: '/var/lib/buildbot/slaves/debian-stretch-amd64-1/miniconda/conda-bld/noarch/migen-0.5.dev-py_121+gitd8860cd.tar.bz2'.

20:50 <sb0> no development session would be complete without conda breakage

20:59 <sb0> _florent_, why is XilinxDDROutputImpl for spartan-6 using DDR_ALIGNMENT="NONE"?

21:00 <sb0> I think it should be C0

21:04 <GitHub7> [migen] sbourdeauducq pushed 1 new commit to master: https://git.io/v7Am2

21:04 <GitHub7> migen/master 11aa1be Sebastien Bourdeauducq: xilinx: change Spartan-6 DDR output alignment to C0

21:06 <bb-m-labs> build #167 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/167