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kristianpaul>
fpgaminer: Hi
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kristianpaul>
Your Verilog_Xilinx_Port works with a 50Mhz clock right?
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kristianpaul>
I just got in sinthezised on my M1, but i'n sending data (64bits) and got no reply
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kristianpaul>
i just noticed you use hash_clk for serial_transmit clock
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kristianpaul>
but this is set to 50Mhz freq
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kristianpaul>
but main pll is dividing clock freq by 2 it seems
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kristianpaul>
ah this could ne, that i should enable the commented line with CLK2X..
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kristianpaul>
btw your code is very nice well documented ;-)!!
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kristianpaul>
ah indeed thats the problem, ClkFrequency should be 25000000