00:01 <Joerg-Neo900> long story truncated: until e.g. Neo900 could even start to ponder usingf that leete new chip, usually a 3 to 7 years will pass by after initial press release announcement of the chip

00:03 <Joerg-Neo900> and 5G they don't even have the protocol specs settled and prettyprinted, so nobody within a sane mind would star developing a massmarket-targeted chip for it

00:03 <Joerg-Neo900> start*

00:03 <Joerg-Neo900> hi houkime

00:05 <houkime> hi joerg. Long time no see. Checking irclog you had a bad time(

00:09 <Joerg-Neo900> houkime: you should provide a "clean" layout placement draft so the product devs and circuit design engineers (werner, me) can review and catch the inferred 5 lacking special placement notes for a few sensors etc. Werner and me tried hard to add all that metainfo into the whitepapers and the schematics in "NOTE:"s, but probably we missed a few

00:11 <houkime> What exactly do you mean by "clean"?

00:11 <Joerg-Neo900> I didn't look into any placement files yet, so maybe they are already existing and "clean" and I'm just not aware. Anyway either way we need a few hours "interactive" chat with you Werner me to make sure we're on same page with all that stuff

00:13 <Joerg-Neo900> >>What exactly do you mean by "clean"?<< noting special, that's why I placed it in "ticks". Just needs to be appropriate document so werner and me can understand what you're doing regarding placement

00:13 <Joerg-Neo900> afk

00:14 <houkime> ok. I guess then it needs to be a documentation regarding reasoning behind placing components one way and not another.

00:15 <houkime> I thought about writing stuff this summer but never got to it evidently. My bad.

00:19 <houkime> There're multiple .fods tables with placement calculations though they don't cover or explain everything.

02:00 <Joerg-Neo900> hey, don't you think this is a tad over the top documetation wide? for pretty much 90+% of components, placment is trivial, for another 5% it's self evident

02:01 <Joerg-Neo900> unless some placement consideration has impact to *all* at once, in which case whe should have had this chat much earlier. So let's hope this won't bite our rear

02:02 <Joerg-Neo900> wise*

03:52 <houkime> right now there is placement itself (kicad pcb file) which is missing stuff on the upper (mainly because display connector esd protection was geometrically not feasible with parts that are in sch), fods calculations and issues in notabug repository that cover current and some past challenges and considerations.