ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at
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* Sarayan waves
<Sarayan> hi everyone
<whitequark> hi Sarayan !
<Sarayan> when I have a two-bit "mode" value, and I rotate between the four modes, but I don't care about the actual bit values of the mode, is there a way to leave the choice of values to the compiler?
<whitequark> do you want them to be "optimal", or just arbitrary?
<Sarayan> optimal, if at all possible
<whitequark> it's not really possible because you can't really express that in verilog or yosys
<whitequark> it's a hard problem because it spans so many abstraction layers
<whitequark> the LUT mapper is the place where you know if the encoding is optimal, but by that point most representation info has been lost
<Sarayan> ok
<Sarayan> so I'll put in values and whatev'
<whitequark> yep
<whitequark> then you can permute them later
<whitequark> i did that for boneless
<Sarayan> hmmm, I'd need to make them symbolic for that
<Sarayan> python enum is the thing I need to do, lemme do it then
<whitequark> yep
<Sarayan> should I call the input clock clk or sync?
<whitequark> clk
<whitequark> sync is the name of the domain
<whitequark> (default)
<whitequark> the clock name is <domain>_clk, except for sync, where it's just clk
<Sarayan> I'm... not sure what it means
<whitequark> let me expand
<Sarayan> please
<whitequark> a domain is essentially a flip-flop control set, i.e. clock signal, reset signal (if any), enable signal (if any)
<Sarayan> ok
<whitequark> the "default" domain, the domain where you put synchronous logic in modules that only work in a single domain (have no CDC inside), is called "sync"
<whitequark> in that domain, the conventional name for the signals is "clk", "rst" and "en"
<whitequark> in any other domain, say called "foo", the conventional name for the signals is "foo_clk", "foo_rst", "foo_en"
<Sarayan> ok
<whitequark> nmigen will assign that for you when you create a ClockDomain object
<whitequark> it mostly matters when you're reading verilog output
<whitequark> or rtlil
<Sarayan> ok
<Sarayan> argh ImportError: cannot import name 'enum' from 'enum' (/usr/lib/python3.8/
<Sarayan> ok fixed
<Sarayan> TypeError: '>' not supported between instances of 'smode' and 'int'
<Sarayan> Signal(Enum) doesn't seem to work
<Sarayan> maybe due to python 3.8
<Sarayan> ahh no, you can't have a reset value that's an enum value
<whitequark> try IntEnum
<whitequark> reset value as enum value, hm
<whitequark> this was added in
<Sarayan> ok, works with an IntEnum
<Sarayan> ok, current speed (in python) is 1:1000
* ZirconiumX waves to Sarayan
<ZirconiumX> You simulating the 6502 machine?
<Sarayan> No, I'm doing something simpler because not schematics-derived to train myself into using nmigen better
<Sarayan> the k053252, a konami arcade video timings generator
<whitequark> Sarayan: sounds about right for python
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