ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen
<awygle> does anybody else find the endianness of Cat confusion?
<awygle> *confusing
<awygle> i expected the first argument to be the most significant bits (admittedly, without reading the docs, which clearly explain the behvaior)
* zignig does, it seems to be the wrong way around to me.
<ktemkin> yeah; that can be surprising — but the rationale is to keep initialization order consistent with python
<ktemkin> and that makes sense to me; even if I had to quiet the gateware section of my brain a bunch at first :)
<awygle> i'm not really sure what you mean by "keep initialization order consistent with python", can you elaborate?
<ktemkin> s/initialization/declaration
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<ktemkin> e.g. imagine you’re declaring a python list with elements such that `x = [‘a’, ‘b’, ‘c’];`
<ktemkin> x[0] would be ‘a’
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<zignig> awygle: what does sop and eop do ?
<awygle> zignig: "start of packet" and "end of packet"
<zignig> ah coolies. thanks.
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<peepsalot> basic question about the blinky example. can multiple resources (slice notation?) be requested in a single call, if the board has an array of LEDs? https://github.com/nmigen/nmigen/blob/master/examples/board/01_blinky.py#L10
<ZirconiumX> peepsalot: no, unfortunately
<ZirconiumX> You need to request them in a loop
<peepsalot> ok
<peepsalot> my 8bit blinky is working! :D
<peepsalot> it really is like magic
<peepsalot> although, is it supposed to just stop after running for a bit?
<peepsalot> a watchdog timeout or something?
<Degi> When I conditionally set a signal to something, will it automatically return to its reset value when the condition is false?
<_whitenotifier-3> [nmigen] mszep commented on issue #327: pysim: option to capture simulation output in a python object - https://git.io/Jvgrc
<samlittlewood> Degi: combinatorial? yes.
<Degi> Hm how about synchronous? I guess then it'll stay at the value it is set to?
<peepsalot> really weird, it seems to be continuing much longer the 3rd or 4th time i programmed it, hasn't stopped this time
<Sarayan> Damn, I need to stop typing "when" instead of "with"
<Sarayan> Nope, I don't know how to implement this thing, damn
<Sarayan> looks like I can't read a ram in less than 3 cycles, great
<Sarayan> oh well
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<samlittlewood> Degi: yes - for synchronous, (but that new value will only be seen by further logic on the next cycle)
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<Sarayan> what is a synchronous, transparent ram? What does transparent actually mean?
<daveshah> Transparent means that if a read and write happen in the same cycle, the read data is the new written data rather than the previous data
<daveshah> aka read after write
<daveshah> From a circuit point of view, imagine the register being on the address input rather than on the read data output
<Degi> Is it possible to change the sync clock signal of one submodule?
<Sarayan> ah thanks
<Sarayan> there no way to tell "I won't read and write at the same time ever"?
<daveshah> Don't think so, although if you don't care about that case then non-transparent is always a better choice
<Sarayan> ok
<Degi> If I want to use a module using the sync domain in two different domains, is there some way to do that without rewriting the module?
<Sarayan> I'm surprised domain and transparency is a property of the port and not the memory itself
<Sarayan> I suspect it makes zero sense to have these different
<Degi> Hm probably true. It could maybe be used to reduce power consumption, though otherwise I guess sync could be run at the highest used frequency
<Sarayan> I don't think there's a fpga which would be happy to have different modes
<Sarayan> and a CDC at the access ports of a ram in an asic, *ouch*
<Sarayan> if I m.d.sync += ram_read_port.addr.eq(...) at time t, I'll have the data in .data at t+2, right?
<Degi> Hmm IIRC according to the ecp5 datasheets, yes
<Sarayan> at t+1 the address port is set, at t+2 you get the data, and if you latch it you have it outside at t+3
<Degi> Nice, I wrote a test for a FIFO... Lets see how many MHz it can do
<Degi> Is it a bad idea to clock sync out of spec? I've only done that with separate clock domains before...
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<awygle> Degi: you want DomainRenamer
<awygle> to change a module using sync to use something else without rewriting
<Degi> Thanks!
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<_whitenotifier-3> [nmigen-boards] peteut opened pull request #49: Add Digilent Genesys2 board - https://git.io/JvgDS
<_whitenotifier-3> [nmigen] whitequark commented on issue #327: pysim: option to capture simulation output in a python object - https://git.io/JvgS0