<awygle>
i don't have any disdain for academia, i just have caution for both academic and corporate open source projects, since both are usually attempting to satisfy different objectives than just "make the best software"
<whitequark>
(doesn't yosys count as academic *and* corporate?)
<awygle>
yosys started out as academic but i wouldn't say it is now
<awygle>
and again, i'm not saying that _all_ academic software is bad, just that much of it is not good (as indeed most software is not good)
<awygle>
c.f. VPR - good research tool, apparently not great for practical PnR. which is fine
<awygle>
but not very helpful if you want to do PnR on an Artix
<whitequark>
i'm not actually sure what kind of research it's good for
<awygle>
it seemed targeted at fpga design, so you could try out a bunch of architectures before designing your chip?
<whitequark>
presumably if you're working on something as concrete as FPGA architectures, you're going to tape them out at some point
<whitequark>
but VPR seems unsuited to doing PnR on basically any actually shipping FPGA
<whitequark>
so... where's all these FPGAs VPR helped design?
<awygle>
fair point
<whitequark>
anyway, i agree it's interesting and worth investigating
<awygle>
i'ma read the papers
<awygle>
lol this paper has a great graph of synthesis time in yosys vs a "commercial tool"
<whitequark>
hahaha
<ZirconiumX>
whitequark: Altera bought them :P
<ZirconiumX>
Remember: Quartus' PnR backend is a very heavily modified VPR
<whitequark>
oh huh
<whitequark>
I retract my statement
<ZirconiumX>
You can even see the VPR function names in the debug symbols that Quartus ships with
<ZirconiumX>
To be honest, I have learned much in the way of FPGA architecture thanks to the literature review of LUT mapping algorithms.
<ZirconiumX>
Unfortunately it raises mostly questions than answers
<ZirconiumX>
e.g. what constitutes a fracturable LUT
<ZirconiumX>
I think we can all agree that iCE40 doesn't have them and modern Xilinx and Intel do (excepting the Cyclone 10LP)
<ZirconiumX>
But I think you could make an argument for the ECP5 having fracturable LUTs.
<ZirconiumX>
For example, a Xilinx CLB is two LUT5s with all inputs shared, with a mux on their outputs to get LUT6
<ZirconiumX>
And an Intel ALM is four LUT4s connected to a two-bit mux (roughly)
<ZirconiumX>
And it has eight inputs to allow packing of two independent LUT4s
<ZirconiumX>
Or two LUT5s with only two shared inputs
<ZirconiumX>
Now, an ECP5 slice is two LUT4s each with independent inputs, plus a mux on their outputs with its own selector input for LUT5
<ZirconiumX>
And I could argue that a slice is a fracturable LUT
<ZirconiumX>
... This is mostly me rambling based on a paper I read on fracturable LUTs that used VPR. Why do I always establish the topic tangent link after the tangent?
<awygle>
Wow, these papers are actually _really_ interesting
<awygle>
And seem very practically minded
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<zignig>
awygle: are you looking at the differential-dataflow papers ?
<awygle>
zignig: my comment was about the lgraph papers
<awygle>
but i have read some of the differential dataflow ones as well
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[nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/Jvltb
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[nmigen/nmigen] whitequark 3fd7fe7 - Travis: test on Python 3.8.
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[nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/Jvltx