ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at
<awygle> this is very interesting as a concept, and something i've thought about before
<awygle> although it's academic, so i'm somewhat skeptical about its practicality and functionality
<whitequark> interesting
<whitequark> i don't share the disdain for academia; i think commercial tools are no less subject to pathological incentives
<awygle> i was thinking about whether something like could be applied to synthesis/simulation
<awygle> i don't have any disdain for academia, i just have caution for both academic and corporate open source projects, since both are usually attempting to satisfy different objectives than just "make the best software"
<whitequark> (doesn't yosys count as academic *and* corporate?)
<awygle> yosys started out as academic but i wouldn't say it is now
<awygle> and again, i'm not saying that _all_ academic software is bad, just that much of it is not good (as indeed most software is not good)
<awygle> c.f. VPR - good research tool, apparently not great for practical PnR. which is fine
<awygle> but not very helpful if you want to do PnR on an Artix
<whitequark> i'm not actually sure what kind of research it's good for
<awygle> it seemed targeted at fpga design, so you could try out a bunch of architectures before designing your chip?
<whitequark> presumably if you're working on something as concrete as FPGA architectures, you're going to tape them out at some point
<whitequark> but VPR seems unsuited to doing PnR on basically any actually shipping FPGA
<whitequark> so... where's all these FPGAs VPR helped design?
<awygle> fair point
<whitequark> anyway, i agree it's interesting and worth investigating
<awygle> i'ma read the papers
<awygle> lol this paper has a great graph of synthesis time in yosys vs a "commercial tool"
<whitequark> hahaha
<ZirconiumX> whitequark: Altera bought them :P
<ZirconiumX> Remember: Quartus' PnR backend is a very heavily modified VPR
<whitequark> oh huh
<whitequark> I retract my statement
<ZirconiumX> You can even see the VPR function names in the debug symbols that Quartus ships with
<ZirconiumX> To be honest, I have learned much in the way of FPGA architecture thanks to the literature review of LUT mapping algorithms.
<ZirconiumX> Unfortunately it raises mostly questions than answers
<ZirconiumX> e.g. what constitutes a fracturable LUT
<ZirconiumX> I think we can all agree that iCE40 doesn't have them and modern Xilinx and Intel do (excepting the Cyclone 10LP)
<ZirconiumX> But I think you could make an argument for the ECP5 having fracturable LUTs.
<ZirconiumX> For example, a Xilinx CLB is two LUT5s with all inputs shared, with a mux on their outputs to get LUT6
<ZirconiumX> And an Intel ALM is four LUT4s connected to a two-bit mux (roughly)
<ZirconiumX> And it has eight inputs to allow packing of two independent LUT4s
<ZirconiumX> Or two LUT5s with only two shared inputs
<ZirconiumX> Now, an ECP5 slice is two LUT4s each with independent inputs, plus a mux on their outputs with its own selector input for LUT5
<ZirconiumX> And I could argue that a slice is a fracturable LUT
<ZirconiumX> ... This is mostly me rambling based on a paper I read on fracturable LUTs that used VPR. Why do I always establish the topic tangent link after the tangent?
<awygle> Wow, these papers are actually _really_ interesting
<awygle> And seem very practically minded
_whitelogger has joined #nmigen
<zignig> awygle: are you looking at the differential-dataflow papers ?
<awygle> zignig: my comment was about the lgraph papers
<awygle> but i have read some of the differential dataflow ones as well
<_whitenotifier-3> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-3> [nmigen/nmigen] whitequark 3fd7fe7 - Travis: test on Python 3.8.
<_whitenotifier-3> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-3> [nmigen/nmigen] whitequark 71d9eea - Travis: prune dependencies.
<_whitenotifier-3> [nmigen] Success. 82.24% (+0.11%) compared to 57b08db -
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing 57b08db...3fd7fe7 -
<_whitenotifier-3> [nmigen] Success. 82.24% remains the same compared to 3fd7fe7 -
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing 3fd7fe7...71d9eea -
<_whitenotifier-3> [nmigen] Success. 82.53% (+0.41%) compared to 57b08db -
<_whitenotifier-3> [nmigen] Success. Absolute coverage decreased by -0.3, only covered lines were removed -
<whitequark> hm
<_whitenotifier-3> [nmigen] Success. 82.53% remains the same compared to 3fd7fe7 -
<_whitenotifier-3> [nmigen] Success. 82.42% (+0.29%) compared to 57b08db -
<_whitenotifier-3> [nmigen] Success. 82.42% remains the same compared to 3fd7fe7 -
jfng has quit [Quit: killed]
emily has quit [Quit: killed]
emily has joined #nmigen
<cr1901_modern> Is there an nmigen equivalent list comprehension to the linked code/lines?
<zignig> awygle: URL pls.
jfng has joined #nmigen
<whitequark> cr1901_modern: no, but you can just use a loop
<whitequark> for i in range(...): with m.If(... i ...): etc
<_whitenotifier-3> [nmigen/nmigen] whitequark tagged 71d9eea as v0.2
<whitequark> jfng: ^
<cr1901_modern> okay, loop it is. I was probably being cute when I wrote that anyway
<whitequark> i mean, that's just the general change in approach to control flow between migen and nmigen
<zignig> right ... friday night meta ..
<zignig> can nmigen greade any construct and give it a score from 0->wrong to 16->fully zipcpu weird <$GOD> complient.
<zignig> anything > 6.42287 makes it in;
momota has joined #nmigen
momota has left #nmigen [#nmigen]
Asu has joined #nmigen
<awygle> zignig: scroll to the bottom
Stary has joined #nmigen
Asu has quit [Ping timeout: 272 seconds]