ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen
<awygle> will do (eta ~3 hours)
<whitequark> the main issue with using WB4 here is that it's just too complex
<whitequark> something like an UART FIFO doesn't need half of its signals
<awygle> true
<awygle> i find it hard to believe that axi-stream avoids this complexity problem
<awygle> but again, haven't looked
<whitequark> axi-stream is basically 4 signals
<whitequark> it's completely unlike normal axi, which is extremely complex
<whitequark> data, valid, ready, last
<whitequark> hm
<whitequark> now that i look again, it looks like it supports things like sparse data streams, which means it's a bit more complex than that; not sure how i missed it before
<whitequark> and the payload should be an integer number of octets, which is also an issue
<whitequark> still, it has no address or select signals, which is already better than WB
<_whitenotifier-3> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JvZFQ
<_whitenotifier-3> [nmigen/nmigen] whitequark 3b67271 - test_build_res: fix after commit 3e2ecdf2.
<_whitenotifier-3> [nmigen] Success. 82.3% (+0.11%) compared to 3e2ecdf - https://codecov.io/gh/nmigen/nmigen/commit/3b6727152ed79cc1857ce20c38f27207b8cc9fd7
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing 3e2ecdf...3b67271 - https://codecov.io/gh/nmigen/nmigen/commit/3b6727152ed79cc1857ce20c38f27207b8cc9fd7
<_whitenotifier-3> [nmigen] Success. 82.30% (+0.11%) compared to 3e2ecdf - https://codecov.io/gh/nmigen/nmigen/commit/3b6727152ed79cc1857ce20c38f27207b8cc9fd7
<_whitenotifier-3> [nmigen] Success. 82.18% remains the same compared to 3e2ecdf - https://codecov.io/gh/nmigen/nmigen/commit/3b6727152ed79cc1857ce20c38f27207b8cc9fd7
<_whitenotifier-3> [nmigen] awygle commented on issue #181: Reconsidering AsyncFIFO and resets - https://git.io/JvZj2
<_whitenotifier-3> [nmigen] whitequark commented on issue #181: Reconsidering AsyncFIFO and resets - https://git.io/JvZjr
<_whitenotifier-3> [nmigen] awygle opened issue #317: Stream Abstraction for nmigen.lib - https://git.io/JvZjd
<_whitenotifier-3> [nmigen] awygle commented on issue #181: Reconsidering AsyncFIFO and resets - https://git.io/JvZjx
<awygle> i like avalon-st more than axi4-stream, based on a relatively rapid review of both
<awygle> i think the stuff it provides over and above the simplest possible thing are more useful than those provided by axi4-stream
<awygle> we should probably start with that simplest possible thing
<_whitenotifier-3> [nmigen] whitequark commented on issue #317: Stream Abstraction for nmigen.lib - https://git.io/JvneJ
<_whitenotifier-3> [nmigen] awygle commented on issue #317: Stream Abstraction for nmigen.lib - https://git.io/Jvne6
<_whitenotifier-3> [nmigen] whitequark commented on issue #317: Stream Abstraction for nmigen.lib - https://git.io/JvnvC
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<_whitenotifier-3> [nmigen] mithro commented on issue #317: Stream Abstraction for nmigen.lib - https://git.io/JvnfC
<_whitenotifier-3> [nmigen] enjoy-digital commented on issue #317: Stream Abstraction for nmigen.lib - https://git.io/Jvnfg
<_whitenotifier-3> [nmigen] enjoy-digital commented on issue #317: Stream Abstraction for nmigen.lib - https://git.io/JvnJP
<Sarayan> hmmmm
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<_whitenotifier-3> [nmigen] whitequark commented on issue #317: Stream Abstraction for nmigen.lib - https://git.io/JvnmZ
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<_whitenotifier-3> [nmigen-soc] jfng opened pull request #7: Add support for extending the address space of a memory map - https://git.io/Jvn3T
<_whitenotifier-3> [nmigen-soc] codecov[bot] commented on pull request #7: Add support for extending the address space of a memory map - https://git.io/Jvn3L
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<awygle> whitequark: so if i was gonna take the serial branch of nmigen-stdio and try to get it de-branched, what would that take?
<electronic_eel> awygle: de-branched? do you mean merged into master or something else?
<ZirconiumX> I presume "mainlined" here
<awygle> Yes