* zignig
managed half of a FIFO'd uart. is bashing my head against FIFO -> TX.
<awygle>
lol i literally just wrote something exactly like this
<awygle>
didn't formally verify it tho
<awygle>
should learn about nmigen formal at some point
<zignig>
indeed , I think formal + nmigen will be a serious draw card for developer ( amongst other things)
<zignig>
awygle: does you fifo'd uart work ? , have you published the code ?
<awygle>
i was talking about the skid buffer
<zignig>
haha :)
<awygle>
my UART works but i haven't glued it to a FIFO yet. i do have a streamified FIFO and the UART takes a stream, so i could try that real quick i spose...
<zignig>
sounds interesting, having streamy modules that you can just glue together would make pipeline development easier. (I assume that is the idea).
<awygle>
yup
<zignig>
having ... switches , backpressure , converters and other fluid metaphores would be awesome.
<zignig>
thinking GNU radio Blender-node style interfaces ...
<awygle>
yeah that's approximately the idea
<awygle>
mk i stuck the FIFO between the UART TX and RX and the UART still works
<zignig>
hooray !
<awygle>
it's a bit hard to evaluate since the addition of the fifo in the loopback doesn't change the behavior at all lol
<zignig>
have a switch that activates the empty only when it's full.
<zignig>
then you will know.
<zignig>
anyway.. meeting to attend... ;)
<awygle>
i turned off FWFT and now there's a one-character delay
<awygle>
so i call this success
<awygle>
that feels validating lol
<awygle>
enjoy your meeting
<zignig>
thanks ;P
<zignig>
have you published your code on github or is it still at the "futzing about" stage? ...
<awygle>
i have a repo, but it's not up to date currently. i can push to it if you're interested