ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at
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<awygle> hmm how can I make a warning or a lint...
<zignig> awygle: in what context , I tend to use print() :0
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<awygle> zignig: i want to warn the user if they do something which is ill-advised. something like DeprecationWarning
<zignig> awygle: <sarc> or just let darwin sort it our </sarc>
<zignig> *out
<awygle> ahhh thank you!
* awygle is bad at python
<zignig> awygle: python has lots of crinkly edges , but it is good for building stuff.
<zignig> what are you trying to build ?
<awygle> working on a stream abstraction for nmigen
<awygle> gonna propose it to whitequark once i have something i'm happy with, which i'm getting closer to
<zignig> coolies, pls read , as it clarified much stuff for me.
* zignig managed half of a FIFO'd uart. is bashing my head against FIFO -> TX.
<awygle> lol i literally just wrote something exactly like this
<awygle> didn't formally verify it tho
<awygle> should learn about nmigen formal at some point
<zignig> indeed , I think formal + nmigen will be a serious draw card for developer ( amongst other things)
<zignig> awygle: does you fifo'd uart work ? , have you published the code ?
<awygle> i was talking about the skid buffer
<zignig> haha :)
<awygle> my UART works but i haven't glued it to a FIFO yet. i do have a streamified FIFO and the UART takes a stream, so i could try that real quick i spose...
<zignig> sounds interesting, having streamy modules that you can just glue together would make pipeline development easier. (I assume that is the idea).
<awygle> yup
<zignig> having ... switches , backpressure , converters and other fluid metaphores would be awesome.
<zignig> thinking GNU radio Blender-node style interfaces ...
<awygle> yeah that's approximately the idea
<awygle> mk i stuck the FIFO between the UART TX and RX and the UART still works
<zignig> hooray !
<awygle> it's a bit hard to evaluate since the addition of the fifo in the loopback doesn't change the behavior at all lol
<zignig> have a switch that activates the empty only when it's full.
<zignig> then you will know.
<zignig> anyway.. meeting to attend... ;)
<awygle> i turned off FWFT and now there's a one-character delay
<awygle> so i call this success
<awygle> that feels validating lol
<awygle> enjoy your meeting
<zignig> thanks ;P
<zignig> have you published your code on github or is it still at the "futzing about" stage? ...
<awygle> i have a repo, but it's not up to date currently. i can push to it if you're interested
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<zignig> I am that would be great, my current noodling in nmigen is contained in
<zignig> as for your previous question about uart encapsulation have a look at and
<zignig> I have used slip with a extra byte on the frame delimiter so I had 255 different streams, I kept console on id 0.
<awygle> yeah i've used slip in the past as well
<awygle> that 2x worst case overhead is a bummer
<awygle> cobs is better for that but you have to pre-buffer it, and ideally limit max packet size
<zignig> correct on both counts, but as your packet size aproaches infinity it doesn't matter ;P
<awygle> ignore the several half-finished stream classes :p
<zignig> thank you, will have a look.
<awygle> np, let me know what you think
<awygle> headed off to bed now, later
<zignig> gnite
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<awygle> good morning
<ZirconiumX> Morning awygle
<_whitenotifier-3> [nmigen] anuejn deleted a comment on issue #207: Enhancing the FSM sub-language -
<anuejn> ZirconiumX: thanks for pointing out :)
<_whitenotifier-3> [nmigen] anuejn commented on issue #207: Enhancing the FSM sub-language -
<awygle> starting to feel really good about streams
<awygle> wish I could keep working on them instead of going to work... ah well
<awygle> ... anybody else unable to reach any repositories on github?
<daveshah> Having intermittent errors here
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<awygle> trying to learn about nmigen-soc and rapidly coming to the realization that i need a "socs for dummies" intro >_> oops
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