ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at
<_whitenotifier-3> [nmigen] whitequark commented on issue #254: Find solution to translate values to strings for Symbiyosys vcd files -
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<cr1901_modern> Huh, part of me is surprised, but another part isn't that you're on IRC, Sam :P
<samlittlewood> :) yeah - not a regular, but came by as I am poking around with glasgow & nmigen
<cr1901_modern> Thanks for your help w/ the CM32p module, btw
<samlittlewood> np - v. glad to help!
<awygle> whitequark: do Records have a guaranteed stable representation? they subclass Value so i assume one can Cast them to Signal, right?
<awygle> context: "how do i take a stream which uses a record for its payload type and connect it to a stream whose payload is half as wide, or twice as wide?"
<awygle> i could do twice as wide with sub-records, but i don't know how to do half as wide in a generic way unless there's a way to crunch on the bits of the record directly (and even then i gotta figure out how/if to reassemble them afterwards, but that's solveable)
<awygle> also curious where you ended up with this inquiry: and whether you have opinions on uart<->??? bridges
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<anuejn> When i have nested state machines in nmigen, is there a way to set the next state of the outer FSM?
<anuejn> & is the inner FSM reset, when its state in the outer FSM is entered?
<anuejn> is FSM-nesting even a thing you are supposed to do? Or is there a different pattern that is suggested?
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<_whitenotifier-3> [nmigen] anuejn commented on issue #207: Enhancing the FSM sub-language -
<Sarayan> I'm getting a TypeError: Attempted to convert nMigen value to boolean
<Sarayan> on:
<Sarayan> rom1cs = ~(self.i_ab1[18-1:22-1] == 0x00 & self.i_as1 == 0)
<Sarayan> duh
<Sarayan> forgot the m.d.comb
<Sarayan> stupid me
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<Sarayan> the error message though is spectacularly useless
<Sarayan> m.d.comb += rom1cs.eq( ~(self.i_ab1[18-1:22-1] == 0x00 & self.i_as1 == 0))
<Sarayan> failed again, same error
<Sarayan> so I guess I have multiple problams
<Sarayan> is == less binding than & ?
<anuejn> yup
<Sarayan> yep, it is
<awygle> yup
<anuejn> that is your problem
<Sarayan> indeed
<Sarayan> that's sad but wq can't rewrite python's precedence
<anuejn> well... we _could_ do that but it certainly would be quite confusing
<anuejn> (something like
<Sarayan> It would be a bad idea no matter what
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<Sarayan> plus I have a purring cat on in my arms, so there's that
<awygle> Aw, kitty
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<ZirconiumX> anuejn: since nobody answered your question, "no, you shouldn't have nested FSMs" because nMigen is internally a stack and so can only refer to the innermost item of the stack here
<ZirconiumX> Instead pull the inner FSM out to the top level of your module and have the two FSMs communicate over signals
<emily> kitty?
* emily 's ears perk up
* cr1901_modern is a simple man. He sees cat, he pets cat.
<mwk> mewo?
<mwk> *meow
<awygle> Probably worth mentioning the lack of nested FSMs on the FSM issue
<awygle> Unless it's there already
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