<_whitenotifier-3>
[nmigen] whitequark closed issue #286: Misleading error when trying to use self.comb when inheriting from Module - https://git.io/Jv3Vq
<awygle>
whitequark: so i want to have a constant value from which i select bits based on a signal (counter). what's the best way to do that? things i've tried - list of bits [0, 0, 0, 1], Const(0b0001)
<awygle>
the second gives me a TypeError: Cannot index value with (sig counter)
<awygle>
i was a bit surprised i couldn't slice it
<whitequark>
yep
<whitequark>
you can't slice with signals because the width of whatever [] returns must be constant
<whitequark>
or it's not synthesizzable
<awygle>
i see. and python expects you to be able to slice with a variable
<whitequark>
yes, the arguments to [] are arbitrary expression
<whitequark>
*expressions
<awygle>
are submodules supposed to show up in the hierarchy in gtkwave?
<whitequark>
yes
<awygle>
hm. i suspected i was doing something wrong and that only adds more weight to the suspicion. i have top->top in gtkwave, instead of top->top->bus as i expected.
<whitequark>
hm
<awygle>
oh ok resolved, i wasn't passing a pin down the hierarchy correctly
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<Sarayan>
signed shifts as in the vlue shifted is signed or the count is signed?
<Sarayan>
because right shift of signed values with sign extension is rather useful
<Sarayan>
whitequark, if I remove the clockdomain I'm getting AttributeError: 'k053252' object has no attribute 'sync'
<Sarayan>
in:
<Sarayan>
yield Tick(ccu.sync)
<Sarayan>
File "test.py", line 16, in stimulus_proc
<Sarayan>
what should I yield to?
<whitequark>
yield Tick()
<_whitenotifier-3>
[nmigen] ZirconiumX commented on issue #302: nmigen generates invalid RTLIL with negative shifts - https://git.io/Jv3y3
<Sarayan>
works perfectly, thanks
<_whitenotifier-3>
[nmigen-boards] nicolas-robin opened issue #46: PR from m-labs/nmigen-boards not in nmigen/nmigen-boards - https://git.io/Jv3Hg
<ZirconiumX>
Sarayan: right hand side being signed, e.g. x << -3
<Sarayan>
I've seen cases where it would have been useful in software. Doubt it's that useful in hardware though
<_whitenotifier-3>
[nmigen/nmigen-boards] whitequark pushed 6 commits to master [+2/-0/±4] https://git.io/Jv3dr
<_whitenotifier-3>
[nmigen/nmigen-boards] ... and 3 more commits.
<_whitenotifier-3>
[nmigen-boards] whitequark commented on issue #46: PR from m-labs/nmigen-boards not in nmigen/nmigen-boards - https://git.io/Jv3do
<_whitenotifier-3>
[nmigen-boards] whitequark closed issue #46: PR from m-labs/nmigen-boards not in nmigen/nmigen-boards - https://git.io/Jv3Hg
<_whitenotifier-3>
[nmigen] whitequark commented on issue #302: nmigen generates invalid RTLIL with negative shifts - https://git.io/Jv3di
<Sarayan>
Is there an example somewhere I can use on how to go from a nmigen .py a yosis-generated C++ simulation code while not targetting any specific fpga/environment?
<whitequark>
Sarayan: unfortunately not yet, cxxsim is basically alpha code
<Sarayan>
I want C++ for a bunch of reasons (speed, video rendering, interfacing with mame, etc)
<whitequark>
yeah, makes sense
<Sarayan>
so do you recommend I try with yosys alpha code, of that I add some kind of C++ target to nmigen?
<whitequark>
former
<whitequark>
hmmm
<whitequark>
let me try to help you here
<Sarayan>
I'd like to start with the k053252, since it's working and simple and easy to see if the result is correct
<whitequark>
yes. is your module done?
<Sarayan>
yeah
<Sarayan>
small and sweet :-)
<whitequark>
okay, can you post it + explain how you'd like to connect it to mame or w/e?
<whitequark>
then I'll make you an example and hopefully you could follow along on your own with the rest
<Sarayan>
For a start I'd like to be able to run tick() and get the o_* signals, possibly even change the i_ ones
<Sarayan>
from a dedicated C++ program
<Sarayan>
in fact, if I have that I'm good
<Sarayan>
oh, forgot to push the removal of sync. one sec
<whitequark>
alrighty, that's not too hard
<Sarayan>
pushed
<Sarayan>
Yeah, I suspect it's not hard at all, but it's.. obscure
<whitequark>
idneed it is
<Sarayan>
if you run tick() you get the video signals for the overdrive (it's an arcade game) screen configuration, so you can see the outputs moving without having to do any particular protocol
<Sarayan>
I'm not even entirely sure the inputs work, I haven't tested them :-)
<whitequark>
okay, let me build yosys first
<Sarayan>
I'm currently pulling git@github.com:YosysHQ/yosys.git, should I hit your tree instead?
<Sarayan>
looks like it has an appropriate level of complexity
<Sarayan>
and it works, thanks a lot
<whitequark>
:D excellent
<Sarayan>
that means that even once I've added the half dozen missing circuits I should be able to generate one screen in a small amount of time
<Sarayan>
Phil B. has a screen dump done with a logic analyzer, there's no better comparison possible :-)
<whitequark>
sweet!!
<whitequark>
let me know how it goes
<Sarayan>
I shall :-)
<Sarayan>
I suspect it's not really doable on a fpga because the game has 11M of roms on something like 8 or 9 buses, all accessed in parallel, on a 6 or 12 MHz clock. 11M is too much to be inside the fpga, and that's a lot of bandwidth for random access on an external ram
<Sarayan>
mister manages 150MHz max with its external sdram board
<Sarayan>
(aka de-10)
<whitequark>
roms?
<whitequark>
then just use a nor flash
<whitequark>
wait
<whitequark>
*eight buses at the same time*?!
<Sarayan>
well, it's not really buses
<Sarayan>
but for instance the first 68k has its dedicated program rom, the second has its, the two roz chips each have one, the two line chips each have one, the sound cpu has one, the sound chip has one
<Sarayan>
and they can obviously all being read at the same time
<Sarayan>
because they're not connected to each other in the first place, only to the chips that use them
<Sarayan>
so even with a 12MHz clock, that's a lot of accesses
<ZirconiumX>
whitequark: since you mentioned `yield Tick()`, I was going back through some old(er) code which used `yield`. Should there be a DeprecationWarning lint for it?
<_whitenotifier-3>
[nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/Jvsvc
<_whitenotifier-3>
[nmigen/nmigen] whitequark a295e35 - hdl.ast: update documentation for Signal.