00:20 <zignig> m.d.comb += [

00:20 <zignig> self.dut.ack.eq(self.fifo.w_rdy),

00:20 <zignig> self.fifo.w_en.eq(self.dut.rdy),

00:20 <zignig> self.fifo.w_data.eq(self.dut.data),

00:21 <zignig> oops , sorry :(

11:44 <whitequark> awygle: re formal asserts: they can be removed as a part of a yosys script

11:45 <whitequark> this isn't currently done because multi-module formal isn't quite well defined in general yet

13:05 <_whitenotifier-3> [nmigen] jfng commented on issue #312: Assignment to a Record with zero-width fields generates invalid Verilog - https://git.io/JvRzD

15:37 <awygle> I see