15:10 <_whitenotifier-3> [nmigen-boards] whitequark reviewed pull request #49 commit - https://git.io/JvDIV

15:10 <_whitenotifier-3> [nmigen-boards] whitequark reviewed pull request #49 commit - https://git.io/JvDIw

15:10 <_whitenotifier-3> [nmigen-boards] whitequark reviewed pull request #49 commit - https://git.io/JvDIr

15:10 <_whitenotifier-3> [nmigen-boards] whitequark reviewed pull request #49 commit - https://git.io/JvDIo

15:10 <_whitenotifier-3> [nmigen-boards] whitequark reviewed pull request #49 commit - https://git.io/JvDIK

19:42 <Vinalon> Is it possible to have a bi-directional signal which can be set by both a module and its parent(s)? Like, a 'start' bit which gets set by a parent module to request an operation and cleared by the child module when it is done?

19:42 <whitequark> yes, but this will flatten your hierarchy

19:43 <whitequark> in general, this will work if you try to do it, but I would recommend that you use a cleaner solution instead

19:47 <Vinalon> okay, thanks! I guess I've been meaning to learn more about the wishbone bus and proper handshaking anyways

19:49 <whitequark> note that there are lots of wishbone building blocks in nmigen-soc

19:50 <Vinalon> oh cool - I hadn't noticed that repository, thanks

19:53 <Vinalon> It looks like it has an example CSR bus, too - neat!

20:59 <Degi> Are there downsides to a flattened hierarchy?

21:14 <whitequark> there are no downsides to it in addition to, well, it being flattened

21:14 <whitequark> flattening causes a few issues: it makes floorplanning harder, and the hierarchical paths no longer correspond exactly to nmigen hierarchy

21:14 <whitequark> but in many cases those are not major

21:29 <Vinalon> I think I did see a 'flattened hierarchy' warning when I tried to make a shared 'start/done' ALU bit...iirc I treated it like an error because I had trouble getting the module to change the signal back after it had been set by a testbench simulation.

21:33 <Vinalon> and I think all of the child module's signals all got merged into the parent module in the '.vcd' result file. But it sounds like those things don't affect the synthesized design too much?

21:33 <Vinalon> (or I might be misremembering)

21:40 <whitequark> sim troubles: probably a different issue, but could be a bug

21:41 <whitequark> merged: yes, that's what "flattening" means

22:16 <Vinalon> yeah, I figured I was probably doing the 'yield dut.thing.eq(stuff)' call wrong or something. It was nice to have a 'bad code smell' warning to put me back on track.