05:18 <cr1901_modern> whitequark: Dunno why I thought of this tonight, but some misoc (sic)-based designs (artiq) have an interrupt and associated hardware called a "mailbox". What what exactly _is_ a mailbox, and will nmigen have an IP for it?

05:31 <whitequark> cr1901_modern: single element FIFO, more or less

05:31 <cr1901_modern> ahh

05:36 <awygle> compare/contrast with "doorbell" :p

05:37 <cr1901_modern> Yea, there's also a "doorbell" identifier in said designs w/ mailbox

05:38 <awygle> the doorbell is what you ring after you fill up the mailbox

05:39 <cr1901_modern> .oO (They only ever ring the doorbell for a package, that they don't even put in the mailbox. The jerks!)

05:48 <whitequark> lol

05:57 <cr1901_modern> I was sending a bunch of emails out tonight- I realize that I tend to "pipeline" emails like a CPU. I send them all my emails in bulk, and latency hide variable response time by acting on responses as soon as they come in.

05:57 <cr1901_modern> I thought maybe "mailbox" in the hardware sense was a latency-hiding technique.

12:10 <_whitenotifier-3> [nmigen-boards] jchidley commented on pull request #57: Add a board file for Gnarly Grey's iCE40UP5K 'Upduino' board - https://git.io/JvDzk

14:09 <_whitenotifier-3> [nmigen-boards] WRansohoff commented on pull request #57: Add a board file for Gnarly Grey's iCE40UP5K 'Upduino' board - https://git.io/JvDVh

14:46 <Vinalon> Is there a recommended way to access BRAM on an iCE40? And is it the same as accessing memory resources on other types of FPGAs?

15:28 <Degi> Hm as far as I know you use a memory submodule and I think nextpnr? automatically assigns BRAM or memory to it

15:34 <Vinalon> Oh, okay; so if you set up a big Array of Signals, it'll automatically get placed into the FPGA's RAM?

15:40 <whitequark> yosys assigns a BRAM cell or a few to the memory, then nextpnr places it

15:48 <Degi> Vinalon: I think you need a memory for that to work https://github.com/nmigen/nmigen/blob/31cd72c0b6250cb74e001df0e25a013bed17fdf2/nmigen/hdl/mem.py

15:48 <Degi> whitequark: Last time I tried, the FIFOs used 16x4 RAM blocks instead of BRAM, is that because they're faster?

15:49 <Vinalon> Oh, okay; there's a Memory class. Great, thanks!

15:51 <whitequark> Degi: I believe the rules only consider area currently, at least directly

16:00 <Degi> yosys tells me "number of memories: 0" and 1875 of TRELLIS_DPR16x4 for a 30k *8 FIFO and that doesn't look very area efficient in nextpnr.

16:00 <Degi> Lol nextpnr gui just segfaulted on route

16:05 <_whitenotifier-3> [nmigen-boards] jchidley commented on pull request #57: Add a board file for Gnarly Grey's iCE40UP5K 'Upduino' board - https://git.io/JvDor

16:06 <daveshah> Number of memories is about RTLIL memories and should always be 0 for synthesised designs whether or not BRAM is used

16:07 <daveshah> My guess is that it is becoming DPRAM instead of BRAM because it isn't finding a read flipflop

16:09 <daveshah> This decision is made by Yosys not nextpnr

16:09 <daveshah> oh, wq already said that

16:11 <Degi> Ah yes, that makes sense

16:12 <Degi> I changed it to SyncFIFOBuffered and now it shows 2 of DP16KD

16:12 <Degi> Thanks for the suggestion

16:13 <daveshah> Were you using fwft?

16:13 <daveshah> afaik that is the only case that SyncFIFO should create LUTRAM rather than BRAM

16:15 <Degi> What is fwft?

16:15 <daveshah> first word fall-through

16:15 <whitequark> fwft is the default so probably

16:15 <Degi> Oh yes it was enabled by default

16:16 <_whitenotifier-3> [nmigen-boards] jchidley edited a comment on pull request #57: Add a board file for Gnarly Grey's iCE40UP5K 'Upduino' board - https://git.io/JvDor

16:37 <_whitenotifier-3> [nmigen-boards] whitequark commented on pull request #57: Add a board file for Gnarly Grey's iCE40UP5K 'Upduino' board - https://git.io/JvDKs

16:37 <_whitenotifier-3> [nmigen-boards] whitequark reviewed pull request #57 commit - https://git.io/JvDKG

17:18 <_whitenotifier-3> [nmigen-soc] whitequark edited issue #6: Clarify documentation for alignment parameters to mention that it is log2 - https://git.io/JvZvM

17:39 <_whitenotifier-3> [nmigen-boards] jchidley commented on pull request #57: Add a board file for Gnarly Grey's iCE40UP5K 'Upduino' board - https://git.io/JvD62

17:53 <_whitenotifier-3> [nmigen-boards] WRansohoff commented on pull request #57: Add a board file for Gnarly Grey's iCE40UP5K 'Upduino' board - https://git.io/JvD6y

17:55 <_whitenotifier-3> [nmigen-boards] WRansohoff synchronize pull request #57: Add a board file for Gnarly Grey's iCE40UP5K 'Upduino' board - https://git.io/JvMIc

20:40 <_whitenotifier-3> [nmigen-boards] whitequark commented on pull request #57: Add a board file for Gnarly Grey's iCE40UP5K 'Upduino' board - https://git.io/JvDM3

20:50 <_whitenotifier-3> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/JvDMo

20:50 <_whitenotifier-3> [nmigen/nmigen] whitequark 2d1e12d - hdl.ast: implement abs() on values.

21:01 <_whitenotifier-3> [nmigen] Failure. 82.45% (+-0.28%) compared to a0d2798 - https://codecov.io/gh/nmigen/nmigen/commit/2d1e12d00ca13ce6ad92fe145beeaa74925de6ef

21:01 <_whitenotifier-3> [nmigen] Success. 100.00% of diff hit (target 82.72%) - https://codecov.io/gh/nmigen/nmigen/commit/2d1e12d00ca13ce6ad92fe145beeaa74925de6ef

21:01 <_whitenotifier-3> [nmigen] Success. 82.74% (+0.01%) compared to a0d2798 - https://codecov.io/gh/nmigen/nmigen/commit/2d1e12d00ca13ce6ad92fe145beeaa74925de6ef

21:03 <Vinalon> is there a built-in method to sign-extend Signals that don't have a signed Shape?

21:05 <whitequark> yep! signal.to_signed() will return a value that will be sign-extended

21:26 <Vinalon> oh, nice - thanks!