<_whitenotifier-3>
[nmigen] jfng opened issue #335: Records with zero-width fields used as module ports break Yosys - https://git.io/JvPOv
electronic_eel has quit [Ping timeout: 255 seconds]
electronic_eel has joined #nmigen
electronic_eel has quit [Ping timeout: 246 seconds]
electronic_eel has joined #nmigen
peepsalot has quit [Quit: Connection reset by peep]
<Degi>
What does assert defs[sig] is self in ir.py line 396 mean? The stack trace doesn't reference any line in my program besides the one where build is called.
<awygle>
probably that you've assigned to the output of an Instance, iirc
<Degi>
Why do I get a "YosysError: ERROR: Multiple edge sensitive events found for this signal!" when I rename the clock domain of a module (which exclusively uses m.d.sync internally)?
Asuu has joined #nmigen
<ZirconiumX>
Degi: that's generally caused by clock domain conflicts
<Degi>
Like when I try to write a signal from multiple domains?
<ZirconiumX>
Multiple *writes* causes a different error
<ZirconiumX>
But this might be multiple reads from different clock domains
Asu has quit [Ping timeout: 256 seconds]
<Degi>
Hm isn't it okay to read a signal from a different domain?
<ZirconiumX>
Right, so I talked to some people in #yosys
<ZirconiumX>
Essentially it means you've generated an incredibly wacky Yosys process
<Degi>
Hm yeah I'll maybe look into the rtlil
<Degi>
Thanks
<mwk>
look for a process with multiple edge triggers
<ZirconiumX>
(hi mwk)
<mwk>
meow
<Degi>
It's the .il file, right? How do I recognize a process with multiple triggers there?
<mwk>
also if you have asynchronous reset, there's a chance it's causing the problem (it shouldn't, but something could be botched)
<Degi>
Hm I don't think that I have any resets yet
<mwk>
look for a process with multiple "sync posedge ..." or "sync negedge ..." lines
<ZirconiumX>
It would be nice if more detail was given...
<mwk>
(or send me the .il file, I could take a look)
<ZirconiumX>
At line 180/182 there's a cell with multiple syncs
<mwk>
no, sync init doesn't count
<Degi>
I think that's an outdated IL, when nmigen throws that error, it doesn't make any il
<mwk>
yep, yosys -p proc accepts this file just fine
<mwk>
hrm
<mwk>
that's... bad
<Degi>
Yes nmigen doesn't make any build directory
<ZirconiumX>
Degi: Are you using nmigen.back.verilog?
<Degi>
What's that
<ZirconiumX>
How are you writing your files?
<Degi>
Hm I have the python script which at the end calls FPGA.ECP55GEVNPlatform().build(DDRTest(), do_program=True, nextpnr_opts="--timing-allow-fail") where the platform is from nmigen-boards
<ZirconiumX>
Well, first off, nmigen *does* create a build directory
<Degi>
It usually does, but not this time
<ZirconiumX>
But anyway
<ZirconiumX>
Can you add this snippet for me
<whitequark>
if verilog conversion fails the build directory won't get created
<whitequark>
so Degi is right
<ZirconiumX>
from nmigen.back import rtlil; with open("foo.il", "w") as f: f.write(rtlil.convert(DDRTest()))
<ZirconiumX>
(I think that's correct?)
<Degi>
Hm I think I'll make a MCVE first
<whitequark>
yep, that should show the problem here
<whitequark>
the MCVE in this case will be mostly for yourself
<whitequark>
this is a known issue & unfortunately rather challenging to fix
<Degi>
Hm okay
<whitequark>
#6
Franananachi has joined #nmigen
<Degi>
Oh yes now the IL has a sync posedge on clk and rx_ck