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[nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±7] https://git.io/Jffag
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[nmigen/nmigen] anuejn ff6c032 - hdl.rec: make Record inherit from UserValue.
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[nmigen] whitequark closed pull request #357: make Record inherit from UserValue - https://git.io/Jfvci
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[nmigen] whitequark commented on pull request #357: make Record inherit from UserValue - https://git.io/Jffa2
<whitequark>
awygle: thinking back to our "synthesizable vs behavioral" discussion
<whitequark>
the 1st paragraph on Verilator website: "Verilator converts synthesizable (generally not behavioral) Verilog code"
<awygle>
huh, so it does
<whitequark>
I think your definition is morally more correct
<whitequark>
but it seems everyone's using mine
<ktemkin>
(maybe this makes me a poor pedant, but I’ve seen those words used to describe so many subtly-different concepts that they feel so context-dependent as to not have a single prescriptivist definition)
<whitequark>
i'm totally on board with not saying "behavioral" ever again because that's my experience too
<ktemkin>
excepting that I'm inevitably going to wind up using it again without thinking, I agree
Vinalon has quit [Remote host closed the connection]
<Vinalon>
It's great how well the 'pysim' simulator works and how easy it is to use
<Vinalon>
the Python syntax makes it easy to run simulations of arbitrary .elf files running on an SoC, and that's a lifesaver for debugging
<Sarayan>
otoh, it's kinda horribly slow
<Vinalon>
oh - I had chalked that up to running it on a cheapo chromebook...
<Vinalon>
mostly I appreciate the ease of use; when I tried to pick up Verilog, I tended to skip writing tests because it was tedious, and that didn't work out well.
<Sarayan>
ototoh, you can use cxxrtl on yosys and you get an acceleration factor of about 1000x. You have to interface in c++ instead of python though
<Vinalon>
huh, interesting - thanks for the tip. I might be a little ways away from figuring out how to do that, though
<whitequark>
Sarayan: Vinalon: eventually, there'll be nmigen.back.cxxsim with the same interface as pysim
<whitequark>
but it'll be a bit of time before that happens
<awygle>
whitequark: i don't think i really have your definition of behavioral clearly stated in my brain, can you summarize? is it just "not synthesizable"?
<Vinalon>
neat!
<whitequark>
awygle: "not directly corresponding to netlist"
<awygle>
mk
<whitequark>
suppose you do something like `for(i=0; i<4; i++) x += y[i];`
<whitequark>
this is quite possibly synthesizable because HLS exists
<whitequark>
but it exists on a higher level of complexity than a netlist
<awygle>
sure
<whitequark>
many people would call that code "non-synthesizable" anyway, but i think my definition is more precise
<Sarayan>
the design is in via6522.py, gen.py generates the yosys commands, which when run generate a c++ sim file with links with main.cc
<Sarayan>
the makefile does the commands for the build
<Sarayan>
It's probably one of the simplest ways to use the nmigen/cxxrtl combo
<Vinalon>
oh cool, thanks
<Sarayan>
that's why nmigen.back.cxxsim is not urgent, the current interfacing is in no way insane
<Sarayan>
oh, port names get a p_ in front and all underscores are doubled for some reason, you have the W and R macros in main.cc that show you how to write and read them