ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at
<_whitenotifier-3> [nmigen] sjolsen commented on pull request #348: back.pysim performance improvements -
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<Vinalon> What's the best way to have a signal (like an I/O pin) follow a clock domain's tick?
<Vinalon> "m.d.comb += pin.o.eq( m.d.sync.clk )" doesn't seem to work
<tpw_rules> like output the clock?
<tpw_rules> i use m.d.comb += pin.o.eq(ClockSignal("sync"))
<Vinalon> ahh, thank you!
<tpw_rules> (there exists ResetSignal, and both can be lvalues)
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<Vinalon> Why might decreasing the width of a signal increase the number of gates that a design uses?
<Vinalon> is it possible for the synthesizer to recognize that equally-sized signals aren't used concurrently and re-use the same resources or something?
<Vinalon> or can it re-use elements which perform N-bit-wide operations?
<tpw_rules> it's more probable that it relaxed some other constraint, like your fmax was higher so it could be lazier with optimization
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<Vinalon> the funny thing is, the timing analysis says it's also slower ¯\_(ツ)_/¯
<tpw_rules> most tools don't try to make it the best it can be
<tpw_rules> they just get it good enough so that it meets the requirements. you can tell it to try harder usually though
<Vinalon> huh, you learn something new every day. Guess it's time to look at the yosys options then
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<_whitenotifier-3> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-3> [nmigen/nmigen] sjolsen 0e40dc0 - back.pysim: Clear pending updates after they are effected
<_whitenotifier-3> [nmigen] whitequark commented on pull request #348: back.pysim performance improvements -
<_whitenotifier-3> [nmigen] whitequark edited a comment on pull request #348: back.pysim performance improvements -
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<_whitenotifier-3> [nmigen] Failure. 82.41% (+-0.34%) compared to 1e74409 -
<_whitenotifier-3> [nmigen] Success. 100.00% of diff hit (target 82.74%) -
<_whitenotifier-3> [nmigen] Failure. 82.69% (+-0.05%) compared to 1e74409 -
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<hhmmnn> hi, i'm looking at nmigen code, and found the following (in
<hhmmnn> timer = Signal(range(delay)) ... with m.If(timer == delay):
<hhmmnn> would that be an off-by-one error?
<ZirconiumX> "range(delay)" makes the signal wide enough to fit delay
<ZirconiumX> So it depends how big it is
<ZirconiumX> It's probably correct to do `with m.If(timer == (delay - 1))` because m.d.sync actions happen the next clock
<anuejn> is it legal to return a module from another elaboratable in the elaborate function instead of creating a new module that only consists of that one module as a submodule?
<hhmmnn> my understanding is that range has the usual Python semantics (i.e. it goes from 0..delay-1), so "timer" could never reach "delay", regardless of timing issues
<ZirconiumX> hhmmnn: I found the line you're referencing. It *might* be an off-by-one error, but in context I don't think it matters
<ZirconiumX> *range* does, yes, but Signal doesn't wrap around if you go above it
<ZirconiumX> Signal(range(X)) means "a Signal wide enough to fit X"
<ZirconiumX> It doesn't mean "a Signal with a maximum of X"
<ZirconiumX> e.g. if X is 48, then Signal(range(X)) will be 6 bits wide and thus go up to 63
<hhmmnn> oh i see what you mean now, "timer" *could* reach "delay", but it depends on the value of "delay"
<hhmmnn> so this is an off-by-one error only of "delay" is a power of two
<ZirconiumX> I think the relevant line should be `Signal(range(delay+1))` for strict safety's sake
<ZirconiumX> Yes
<ZirconiumX> hhmmnn: Implementing exactly the semantics of 0..N-1 would require nMigen to emit a lot of modulus operations in hardware, which would quickly murder area and delay
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<hhmmnn> Zi
<hhmmnn> ZirconiumX: i understand, i just had not considered the case where N is *not a power of two, because it usually is
<hhmmnn> ... in my use cases so far
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<Vinalon> what's the right way to use 'nMigen' at the start of a sentence; "NMigen", or "nMigen"?
<MadHacker> IMHO the latter; you shouldn't change a proper name. Opinions may differ. :)
<Vinalon> yeah, that's what I was leaning towards too; thanks
<Vinalon> What units does the 'sim.add_clock(...)' method accept? Is it Hertz, or the time interval between ticks in seconds or millis or something?
<Vinalon> oh, I should have checked the 'pysim' file: "The process will toggle the ``domain`` clock signal every ``period / 2`` seconds"
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