ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen
<_whitenotifier-9> [nmigen] codecov[bot] commented on pull request #361: vendor: use nextpnr -12k for -12F devices; remove theoretical devices - https://git.io/JfTaR
<_whitenotifier-9> [nmigen] codecov[bot] edited a comment on pull request #361: vendor: use nextpnr -12k for -12F devices; remove theoretical devices - https://git.io/JfTaR
<_whitenotifier-9> [nmigen] codecov[bot] edited a comment on pull request #361: vendor: use nextpnr -12k for -12F devices; remove theoretical devices - https://git.io/JfTaR
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<_whitenotifier-9> [nmigen] whitequark closed pull request #361: vendor: use nextpnr -12k for -12F devices; remove theoretical devices - https://git.io/JfTav
<_whitenotifier-9> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JfTVN
<_whitenotifier-9> [nmigen/nmigen] ktemkin 0e18429 - vendor: use nextpnr -12k for -12F devices; remove theoretical devices
<_whitenotifier-9> [nmigen] whitequark commented on pull request #361: vendor: use nextpnr -12k for -12F devices; remove theoretical devices - https://git.io/JfTVA
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<ZirconiumX> wq: you've talked before about how nmigen.lib.fifo needs vendor false-path attributes. I found the Intel ug_fifo PDF and was wondering if the scfifo/dcfifo were what you were looking for, or if you wanted specifically attributes?
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<chipmuenk> Not sure whether this is the right forum ... but anyway: A student of mine has started on a project for implementing DSP functionality with nmigen, currently he (we) stalls on a simple problem. The following very basic code
<chipmuenk> from nmigen import *
<chipmuenk>
<chipmuenk> from nmigen.cli import main
<chipmuenk> class Blinky(Elaboratable):
<chipmuenk> self.led = Signal()
<chipmuenk>
<chipmuenk> def __init__(self):
<chipmuenk>
<chipmuenk> def elaborate(self, platform):
<chipmuenk> m = Module()
<chipmuenk> counter = Signal(3)
<chipmuenk> m.d.sync += counter.eq(counter + 1)
<whitequark> chipmuenk: please use something like paste.debian.net to share code snippets
<ZirconiumX> Or gist.github.com, or pastebin.com
<ZirconiumX> Or whatever
<chipmuenk> sorry!
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<agg> ( chipmuenk, whatever you tried to share was cut off pretty early on, so you should re-post it using a pastebin and ask your question in here)
<whitequark> chipmuenk: in python, (x,) is a 1-element tuple that contains x
<whitequark> but (x) is just the same as x
<whitequark> try `ports=(top.led,)`
<whitequark> or `ports=[top.led]`
<chipmuenk> ok, thanks, now I run into the expected problem with Yosys' path. I do know the difference between a tuple and its element in python but I'm still doing cargo cult programming w.r.t. nmigen. So "ports" expects a tuple containing top level ports and my example fails because I just pass one signal instead of a tuple containing one signal?
<ZirconiumX> yes
<whitequark> chipmuenk: `ports=` expects any python iterable. tuple or list, typically.
<whitequark> in short, yes.
<whitequark> (we should add better typechecking to that method)
<agg> not the first time someone's had that problem in here :p
<_whitenotifier-9> [nmigen] whitequark opened issue #362: `convert(ports=)` is a hotspot of beginner issues - https://git.io/Jfkkq
<ZirconiumX> As always, usability problems are reportable bugs
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<chipmuenk> Thanks once more for your support, works now. And yes, you're right - the error message "TypeError: Only signals may be added as ports, not (slice (sig led) 0:1)" really confused me.
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<tpw_rules> god i love eurobeat