ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen
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<_whitenotifier-3> [nmigen] programmerjake opened issue #344: run_simulation doesn't call elaborate before trying to set domains - https://git.io/Jv5jI
<awygle> jfng: do you have an example nmigen_soc project that i could look at? still struggling a bit with what does what
<awygle> specifically i'm trying to write an initiator, and can't figure out how to indicate that my interface is one instead of a target
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<jfng> initiator and target interfaces are the same, basically
<jfng> I should update the "hello world" SoC example I linked a few days ago
<jfng> the only difference is that you may also assign a memory map to a target interface
<_whitenotifier-3> [nmigen] The6P4C opened issue #345: Simulation of module with undriven signal causes generated VCD to not contain the signal, but contain an individual signal for each character of the undriven signal's name - https://git.io/Jvdst
<_whitenotifier-3> [nmigen] The6P4C commented on issue #345: Simulation of module with undriven signal causes generated VCD to not contain the signal, but contain an individual signal for each character of the undriven signal's name - https://git.io/Jvds7
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<awygle> the layout is different right? because the directions are different?
<jfng> oh, I forgot about them
<jfng> should we remove directions, or provide two different layouts ?
<jfng> awygle: anyway, directions are only used by Record.connect()
<jfng> assuming .connect() is going to be deprecated, you could just pretend field directions don't exist for now
<jfng> and use wishbone.Interface as is
<awygle> mm, ok, fair enough. i like the existence of directions because... well because python's general typelessness makes me deeply uncomfortable :p but you're right that they're not really being leveraged right now
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<_whitenotifier-3> [nmigen] whitequark commented on issue #345: Simulation of module with undriven signal causes generated VCD to not contain the signal, but contain an individual signal for each character of the undriven signal's name - https://git.io/JvdK6
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<whitequark> awygle: the problem is that records are likely not the right place to introduce directions
<awygle> whitequark: yes, i understand and agree with that. my statement wasn't really an argument for directions in records, just a general lament and an explanation of why "forget about directions here" didn't leap to mind as a solution
<whitequark> ack
<awygle> :)
<whitequark> we really should do something about directions in modules, likely integrated with python typing stuff
<whitequark> i think emily had some ideas in that area
<awygle> i have been typing all my stuff i've been writing recently
<awygle> but don't know how to enforce it
<awygle> (couldn't get mypy to run usefully)
<Sarayan> what's a direction?
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<whitequark> an interface of a module consists of a bunch of signals, used as attributes
<whitequark> some of those signals are assigned inside the module, some outside
<whitequark> assigning a signal both inside and outside is valid but usually undesirable
<whitequark> a "direction" is a way to say where the signal will be assigned. it's similar to the way types work in other languages.
<jfng> for a module, its straightforward: inputs are driven externally, outputs are driven internally
<jfng> but for a record ? it depends on which side you are
<jfng> something I don't like about directions in records is that they are a matter of point of view
<jfng> (matrix seems to reorder my messages...)
<whitequark> that is exactly the problem with directions in records i was talking about with awygle
<Sarayan> so you explicitly says which signals are inputs, which are outputs, and which are just state?
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<whitequark> pretty much
<Sarayan> I'd like that
<Sarayan> conventions are good, but I like when the compiler enforces them
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<Sarayan> how do you implement that, extra parameter when creating the signal?
<whitequark> python type declarations I think
<Sarayan> there's such a thing?
<whitequark> yep
<awygle> there are but it's kind of weird. there are types, and there are type checkers, and there's the typing module. types are part of the langauge, the typing module is part of the standard library, and the type checkers appear to all be 3rd party
<Sarayan> that's... special
<Sarayan> https://docs.python.org/3/library/typing.html seems to be only about prototypes and not variables?
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<whitequark> *sigh* they're special, yes
<whitequark> you can put them in classes but i think that might be undocumented yet
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<awygle> hm, nmigen-soc reset my nmigen installation
<awygle> had to pip -e it again
<awygle> odd, it looks like the versions should be compatible
<jfng> are you using the github version or the pypi version ?
<jfng> iirc on pypi, it requires 0.1
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<awygle> github
<awygle> it just force-installed nmigen == 0.2
<awygle> even though i had the github version of nmigen installed, which should be 0.2-<something> i think
<awygle> then when i did pip -e again everything is fine, nmigen-soc doesn't actually complain
<whitequa1k> awygle: yes, it needs adjustment of the requirements
<whitequa1k> github version of nmigen is 0.3.git which counts as < 0.3 but > 0.2