ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at
<awygle> i'm gonna write a rust 2021 blog post advocating 1) automatic ok-wrapping 2) stabilizing proc_macros in every position and also macros 2.0 3) removing else
<whitequark> i fully support removing if/else in favor of only having a match statement with guard clauses
<anuejn> another issue i encountered was that when i use products.extract to extract a file in a subdirectory it doesnt work
<ZirconiumX> whitequark: would the rotate testcase be in OperatorTestCase or ValueTestCase?
<whitequark> ZirconiumX: latter
<whitequark> anuejn: seems like a bug, can you file it with an MCVE?
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<anuejn> yup
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<awygle> mk now that i've built a hydroponics system in my living room time to go back to work
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<anuejn> do you think there is interest for an automatic stub generator for nmigen records? it would give better autocompletion support but is a rather big hack after all
<whitequark> what's a stub?
<whitequark> how does autocompletion work in vscode?
<anuejn> a .pyi file with type hints
<ZirconiumX> "pfft, it doesn't"
<ZirconiumX> Okay but I have yet to have IntelliSense do something *actually useful* in Python. Rust is great thanks to rust-analyzer, but vscode-python is...lacking
<anuejn> i am not sure for vscode since i use pycharm but i have a stub generator for some xilinx blackboxes and it works rather nice.
<ktemkin> vscode-python works pretty well for me
<whitequark> how would pyi files for records work?
<whitequark> it looks from pep484 that they don't support annotation of local variables
<anuejn> pycharm basically uses typing hints in form of stubs or mypy annotations or magic comments
<ZirconiumX> ktemkin: the vscode-python documentation for Elaboratable is "Elaboratable"
<ZirconiumX> I'm not sure I'd call that "working well"
<ktemkin> well
<anuejn> whitequark: do we need that?
<ZirconiumX> whitequark: I just realised an ugly semantic question with rotates
<ZirconiumX> Consider the following code: `Const(1).rotate_left(1)`.
<ZirconiumX> What should the result be?
<tpw_rules> why is it not 1?
<whitequark> 1
<ktemkin> ZirconiumX: <-- I dunno what you'd expect it to display, there
<ZirconiumX> Even inherited classes would be something
<anuejn> and could we make Elaboratable a ABC with elaborate as an abstract method?
<anuejn> or is there anything thats preventing us from doing so?
<whitequark> hm
<whitequark> it is already an ABC for some reason
<whitequark> anuejn: the idea behind Elaboratable was to make it a "marker class" with minimal impact on user code
<whitequark> which is why it wasn't supposed to have ABCMeta as its metaclass
<ZirconiumX> <-- Mux definitely exists and has documentation, ktemkin
<whitequark> yet, it does, for some reason
<ktemkin> yeah, and I get stuff for it :)
<ZirconiumX> Then I don't know
<ktemkin> ZirconiumX: this is part of the reason why I said "works pretty well for me"; it tries to use whatever tooling you have around to generate those popovers, and I'm not sure it always winds up with the right ones
<ZirconiumX> I don't even know what it's using right now
<anuejn> whitequark: i see but wouldnt marking elaborate be even more markery-ish? I find it always very confusing to write that method on my own rather than having my ide yelling at me that i am not having a proper elaboratable
<ktemkin> ZirconiumX: it might get better if you install jedi; I think it tries to use that for autocomplete if it's around
<anuejn> plus always forgetting to pass plat when i dont need it
<anuejn> ZirconiumX: sounds like you need to tell it where your interpreter (+venv?) lives
<ktemkin> (if it can't find the module for the relevant interpreter; it typically assumes the wrong one and then gets grumpy at you and tells you it can't find your moduels)
<ktemkin> *modules
<ZirconiumX> Default python3 is 3.7.5 and that's what I have selected
<anuejn> is your nmigen installed system-wide?
<_whitenotifier-3> [nmigen] anuejn opened issue #353: BuildProducts extract doesnt work for files in subdirectories -
<_whitenotifier-3> [nmigen] anuejn edited issue #353: BuildProducts.extract() doesnt work for files in subdirectories -
<ZirconiumX> anuejn: yes
<anuejn> hm... wired
<ktemkin> but yeah, not defending it as much as suggesting maybe it'd be better with some config
<ZirconiumX> ktemkin: enabling Jedi gives me a popup with IntelliCoe Python support requiring me to use the Microsoft Python Language Server
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<ZirconiumX> Okay, it turns out VS Code seems to be quite picky with *how* you install your modules system-wide...
<ZirconiumX> I reinstalled it with pip and now I have docs
<ZirconiumX> Just running install is apparently not enough
<ZirconiumX> whitequark: How do I run the test suite?
<whitequark> python3 test
<ZirconiumX> Is the testsuite meant to fail?
<whitequark> nope
<whitequark> CI is green
<ZirconiumX> e.g.
<ZirconiumX> test_distance (nmigen.test.test_lib_coding.GrayCoderTestCase) ... FAIL
<whitequark> oh, that means you aren't set up for yosys formal tests
<whitequark> you need sby and an smt solver
<ZirconiumX> I have SBY but not Yices
<awygle> you can change the template to use z3 or boolector or whatever
<awygle> they all pass
<awygle> hm. i have a Thing which should contain all the information needed to make an hsm
<awygle> but i'm not sure what i should... do with it
<awygle> i could give it an elaborate method
<awygle> but then it'd be a submodule which we Do Not Want
<awygle> maybe i'll just return a big list of uh, instructions or whatever they're called
<whitequark> you can give it a Module
<awygle> yeah, that's not a bad idea either, and much easier to manage than building a huge instruction list
<whitequark> a Module is basically a huge instruction list
<whitequark> so, after I refactor the innards of fragment code to not use term rewriting as it currently does, you could just make it an "inline fragment"
<whitequark> but right now that will likely break horribly in many ways
<awygle> can i print out the huge instruction list that the module is?
<awygle> for testing purposes
<whitequark> sure, print(module._statements)
<awygle> sweet
<Vinalon_> is it possible to use a Value to selectively access valid indices of an Array which contains a mix of nMigen Values and 'None's?
<Vinalon_> I tried 'with m.If( array[ value ] is not None):', but it doesn't seem to work
<whitequark> it is not possible
<whitequark> think of how it would have to be translate
<whitequark> *translated
<Vinalon_> it did seem like a long shot
<whitequark> there was an issue, hmm
<whitequark> #73
<Vinalon_> huh, interesting; time to learn what one-hot encodings are. But an Interface should also work for now, it'll just be a little more verbose.
<Vinalon_> thanks!
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<_whitenotifier-3> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-3> [nmigen/nmigen] whitequark 9055090 - build.plat: don't check for toolchain presence if do_build=False.
<whitequark> aneujn: (assuming you read logs) see above
<_whitenotifier-3> [nmigen] Failure. 82.36% (+-0.34%) compared to 0e40dc0 -
<_whitenotifier-3> [nmigen] Failure. 0.00% of diff hit (target 82.69%) -
<_whitenotifier-3> [nmigen] Failure. 82.64% (+-0.06%) compared to 0e40dc0 -
<_whitenotifier-3> [nmigen] Success. 82.69% (+0.00%) compared to 0e40dc0 -
<_whitenotifier-3> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±2]
<_whitenotifier-3> [nmigen/nmigen] whitequark e9c75f7 - hdl.ast: improve repr() for Shape.
<_whitenotifier-3> [nmigen] Failure. 82.37% (+-0.33%) compared to 9055090 -
<_whitenotifier-3> [nmigen] Success. 100.00% of diff hit (target 82.69%) -
<_whitenotifier-3> [nmigen] Failure. 82.66% (+-0.04%) compared to 9055090 -
<_whitenotifier-3> [nmigen] Success. 82.71% (+0.01%) compared to 9055090 -
<_whitenotifier-3> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±2]
<_whitenotifier-3> [nmigen/nmigen] whitequark 7a08901 - hdl.rec: improve repr() for Layout.
<_whitenotifier-3> [nmigen] whitequark closed issue #326: __repr__ implementation for Layout -
<_whitenotifier-3> [nmigen] whitequark commented on commit 9055090f6552fc40e31e9ac1bc39ab7bcc54b79b -
<_whitenotifier-3> [nmigen] Failure. 82.36% (+-0.36%) compared to e9c75f7 -
<_whitenotifier-3> [nmigen] Failure. 71.42% of diff hit (target 82.71%) -
<_whitenotifier-3> [nmigen] Failure. 82.64% (+-0.07%) compared to e9c75f7 -
<_whitenotifier-3> [nmigen] Failure. 82.69% (+-0.02%) compared to e9c75f7 -
<_whitenotifier-3> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-3> [nmigen/nmigen] whitequark 91d6e4b - fix BuildProducts.extract to work with subdirectories.
<_whitenotifier-3> [nmigen] whitequark closed issue #353: BuildProducts.extract() doesnt work for files in subdirectories -
<_whitenotifier-3> [nmigen] Failure. 82.36% (+-0.34%) compared to 7a08901 -
<_whitenotifier-3> [nmigen] Failure. 0.00% of diff hit (target 82.69%) -
<_whitenotifier-3> [nmigen] Failure. 82.64% (+-0.06%) compared to 7a08901 -
<_whitenotifier-3> [nmigen] Success. 82.69% (+0.00%) compared to 7a08901 -
<awygle> yaaaaay thank you
<awygle> nice work
<whitequark> np
<whitequark> have you looked at #217 since we last discussed it, btw?
<_whitenotifier-3> [nmigen] whitequark commented on issue #254: Find solution to translate values to strings for Symbiyosys vcd files -
<awygle> I haven't no
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<anuejn> whitequark: many thanks :)
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<ZirconiumX> How do I cast a Const to a specific width?
<ZirconiumX> I've been fighting in my testbenches to get C(0b0000001).rotate_left(1) to equal 0b0000010, and it just struck me that it's being interpreted as being one-bit wide
<ZirconiumX> Another thought, which came to mind
<ZirconiumX> If you have an N-bit value X, and do X.rotate_{left,right}(N), you get X again. Should that be warned on? It seems like a bug.
<ZirconiumX> Technically intended behaviour, but then you could replace X.rotate_left(N) with X
<_whitenotifier-3> [nmigen] ZirconiumX synchronize pull request #352: Add rotate by constant -
<_whitenotifier-3> [nmigen] codecov[bot] edited a comment on pull request #352: Add rotate by constant -
<MadHacker> When creating a Signal using an IntEnum (i.e. s=Signal(shape=MyEnum, decoder=MyEnum) is there a straightforward way to get the decoded strings in the vcd to use the hex version of the enum value? context:
<MadHacker> Or do I just need to implement a little decoder function that wraps the enum myself?
<_whitenotifier-3> [nmigen] codecov[bot] edited a comment on pull request #352: Add rotate by constant -
<_whitenotifier-3> [nmigen] codecov[bot] edited a comment on pull request #352: Add rotate by constant -
<ZirconiumX> MadHacker: since Signal supports decoder=<function> you can do that for pysim at least
<_whitenotifier-3> [nmigen] codecov[bot] edited a comment on pull request #352: Add rotate by constant -
<MadHacker> Aye, I mean I know I can do it that way, just wondered if there was a lazier/more "standard" option.
<_whitenotifier-3> [nmigen] ZirconiumX synchronize pull request #352: Add rotate by constant -
<_whitenotifier-3> [nmigen] codecov[bot] edited a comment on pull request #352: Add rotate by constant -
<_whitenotifier-3> [nmigen] codecov[bot] edited a comment on pull request #352: Add rotate by constant -
<MadHacker> I guess it's just lambda x: MyEnum(x).name + "/" + hex(x) anyway.
<_whitenotifier-3> [nmigen] codecov[bot] edited a comment on pull request #352: Add rotate by constant -
<_whitenotifier-3> [nmigen] codecov[bot] edited a comment on pull request #352: Add rotate by constant -
<Degi> Hmm so word_shift is unusable atm, right?
<ZirconiumX> Degi: Seems like it
<Degi> Hm then ill just use switch case and for loop to do that I think...
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<awygle> Word select is broken? Uh oh lol. Gotta change some stuff.
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<awygle> I really like hierarchical state machines
<awygle> I keep thinking I can't express some pattern and then figuring out a really elegant way to do it
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<Degi> Hierarchical state names? In a FSMß
<Degi> ?
<Degi> 90
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<Vinalon> this might sound odd, but are there any cases where a signal being driven from different clock domains should not raise a DriverConflict?
<Vinalon> I have a module which calls 'm.d.sync += self.sig.eq(...)', and that module got passed to another one which called 'm.d.comb += other.sig.bit_select(...).eq(...)'
<Vinalon> and it didn't raise an error, but it seemed like both statements might have ended up acting like combinatorial logic
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<awygle> That should almost certainly be an error
<awygle> Can you produce an MCVE?
<Degi> Hm does bit_select compile properly?