ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at
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<_whitenotifier-3> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-3> [nmigen/nmigen] whitequark ec8386a - back.pysim: fix emission of undriven traces to VCD files.
<_whitenotifier-3> [nmigen] whitequark closed issue #345: Simulation of module with undriven signal causes generated VCD to not contain the signal, but contain an individual signal for each character of the undriven signal's name -
<_whitenotifier-3> [nmigen] Failure. 82.41% (+-0.34%) compared to c79caea -
<_whitenotifier-3> [nmigen] Failure. 0.00% of diff hit (target 82.75%) -
<_whitenotifier-3> [nmigen] Failure. 82.69% (+-0.06%) compared to c79caea -
<_whitenotifier-3> [nmigen] Success. 82.75% (+0.00%) compared to c79caea -
<_whitenotifier-3> [nmigen] whitequark commented on issue #291: Need a way to attach attributes to memories -
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<ZirconiumX> wq: does mean "submit a PR for your branch [instead]?"
<whitequark> ZirconiumX: just in general work together on solving this (since earlier I mentioned I wouldn't be able to help you much; no I can)
<whitequark> *now I can
<ZirconiumX> Ah, okay, thank you WQ
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<vup> is there a way to directly request a connector?
<whitequark> no
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<vup> hmm, I think that could be useful, what do you think?
<vup> or what is the canonical way to have a connector, but also be able to use pins of the connector directly
<vup> ?
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<kc5tja> ZirconiumX: "You don't have to name the signals i_/o_ " -- while true, I still follow Wishbone naming conventions because it really reduces my mental burden when figuring out what connects to what else.
<ZirconiumX> It seems to be nMigen convention for that
<ZirconiumX> Since nMigen is completely unaware of all of this
<kc5tja> Do you mean to write, "there seems to be an nMigen convention for that?" I'm having trouble parsing your response.
<kc5tja> vup: I subclassed a platform, and created my own resources which maps to pins in a connector. See for how I worked around this issue.
<ZirconiumX> kc5tja: yes, though "it" works fine
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<kc5tja> ZirconiumX: Once I'm happy I have a working set of cores that talk to each other, I'll change my code to use Records, maybe even using the library-provided Wishbone functions. Records is still something which feels very alien to me at the moment.
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<ZirconiumX> kc5tja: I generally avoid Records, and since Record.connect is soft-deprecated, I'm not entirely sure what the point of them is
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<vup> kc5tja: hmm yeah, that would work, but that seems similar to using platform.add_resources(..., conn=...) without subclassing
<vup> I was looking for a more "adhoc" way to quickly (without a lot of extra code) access the connector pins
<vup> I guess a workaround could be adding a Resource for each Connector to the platform and just using the Resources then
<vup> however I wasn't sure if there that is the "canonical" nmigen way
<kc5tja> ZirconiumX: Ooh, I wasn't aware of that. Thanks for letting me know. :) I think the intended point, though, was to manage a collection of signals as a logical unit (e.g., an AXI or Wishbone bus, for example).
<kc5tja> vup: Yeah, I haven't found any way of doing that myself. Sorry. Though, in sending you the link that I did, I just noticed a bug (I'm missing an Attrs() declaration in my video resource).
<awygle> yeah Records are a conceptually good idea but the current version are not as useful as it appears at first glance
* ZirconiumX waves to awygle
<awygle> Hallo
<ZirconiumX> Sorry I haven't been that talkative ^^;
<vup> kc5tja: yeah, no worries, I am happy about any input I get
<awygle> S'all good :-)
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<awygle> whitequark: is it possible to access a module's FSM's states from a testbench? so that one could e.g. assert on the wishbone ERR_O signal and print the state in the failure message?
<awygle> (in pysim, not in formal stuff)
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