<Sarayan>
if you have say a charset of 8 bytes per char and 256 chars, that makes your rom depth 0x100*8
<Sarayan>
and you can say use the three bottom bits of the address for y and the top for char number
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<shizuo>
Thanks for that Sarayan, that was the idea, based out of China at the moment and it seems the firewall has noticed me chatting on freenode so I'll log off to stop relentless reconnects.
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<_whitenotifier-9>
[nmigen] whitequark commented on pull request #358: use declarative setuptools config - https://git.io/Jfsn3
<awygle>
morning all
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<whitequark>
hi awygle
<awygle>
hi wq
<ZirconiumX>
Morning awygle
<ZirconiumX>
And WQ
<awygle>
morning ZirconiumX
<ZirconiumX>
Hope things are well
<awygle>
well, you know. we soldier on.
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<whitequark>
awygle: want to read the in-progress docs i'm working on? i need some feedback, i think
<whitequark>
and the current introduction is targeted at "someone like you"
<lkcl>
whitequark: thanks for letting me know about FFSynchroniser and ResetSynchroniser. much appreciated. sorry for not acknowledging earlier: had to go back through the irc logs.
<whitequark>
no problem. these aren't really documented well at the moment. which is why i'm writing documentation that will fix that
<lkcl>
you could almost certainly put that into the NLNet grant, the one that there's room to increase its budget (without going through a 4-month process to apply for a new one)
<lkcl>
i feel NLNet would be more than happy to increase the grant budget by EUR 10k to 12k for you
<whitequark>
I already have a grant for documenting nMigen through other sources, actually
<lkcl>
they view documentation as being extremely important so it's fine to list a milestone for it
<lkcl>
oh great!
<lkcl>
that's really good to hear
<whitequark>
it's more that it's a lot of labor to write good docs
<whitequark>
morally speaking, the test bench that drives a simulated *pos*edge domain should do its work on *neg*edge
<awygle>
?
<awygle>
oh. yeah, i spose that's true.
<whitequark>
because otherwise you get a race!
<whitequark>
there are multiple glasgow tests that fail with the new pysim, and that's actually why
<whitequark>
they were always, in principle, broken
<whitequark>
it's just that old migen and old pysim always resolved this race in a particular order
<whitequark>
which had the side effect of producing confusing vcd files
<whitequark>
because you have no idea what transition was caused by the bench and what was caused by the DUT
<awygle>
yeah
<awygle>
i've run into stuff kind of like this a few times
<whitequark>
it's super annoying, too
<awygle>
i thought there was another big pysim rewrite planned
<whitequark>
nope
<whitequark>
pysim is basically fine as it is
<whitequark>
there's *cxxsim* planned, which has the same interface as pysim but a looot faster
<whitequark>
it has the same race conditions and actually the cxxsim doc recommends updating everything on negedge
<whitequark>
awygle: oh, maybe you mean the "reconsider simulator interface" issue?
<whitequark>
that's not a pysim rewrite per se, it's a change in how we interface with it
<whitequark>
the current interface is actually horrible
<_whitenotifier-9>
[nmigen] whitequark opened issue #377: Our recommended way to write testbenches is racy - https://git.io/Jfso3
<_whitenotifier-9>
[nmigen] whitequark commented on issue #377: Our recommended way to write testbenches is racy - https://git.io/JfsoG
<cr1901_modern>
Feel free to point me to docs, but why is "test bench driving a domain on posedge" a race condition? Shouldn't test bench driving a domain indicate a causal relationship where domain being driven's posedge must happen after the test bench signal posedge?
<_whitenotifier-9>
[nmigen] whitequark edited issue #377: Our recommended way to write testbenches is racy - https://git.io/Jfso3
<whitequark>
cr1901_modern: well, you can't do that
<cr1901_modern>
Ahhh hmmm
<_whitenotifier-9>
[nmigen] whitequark edited issue #377: Our recommended way to write testbenches is racy - https://git.io/Jfso3
<_whitenotifier-9>
[nmigen] whitequark commented on issue #377: Our recommended way to write testbenches is racy - https://git.io/JfsoW