04:27 <zignig> whitequark: are you also looking into making cxxsim export to WASM at some point in the future ?

04:28 <whitequark> probably not

04:39 <zignig> I though it would be cool to have a sim as a portable blob, even platform simulation with somthing like dearimgui

04:40 <zignig> will be looking to try out the wasm yosys and nextpnr this weekend.

04:40 <whitequark> it's not very easy to actually use a wasm blob

04:41 <whitequark> a little bit easier than building and linking a c++ shared object, at the cost of being harder to integrate with other things

04:41 <whitequark> it's not such a good tradeoff, though i expect it'll get better

04:42 <zignig> wasm does seem to gaining interest, and I concur that it will get better. I hope it does not get all bloaty in the process.

04:42 <zignig> perhaps a WASM machine written in nmigen , then you can run yoysys and pnr on itself !

04:43 <awygle> whoof, i haven't seen oMigen code in a long time, it looks very foreign now

04:44 <zignig> awygle: I think your brain is full , too many programming languages.

04:44 <zignig> ;P

04:44 <awygle> tru nuff

04:44 <zignig> basic algebra and times tables fell out when I did engineering maths.

09:16 <MadHacker> It's not too many programming languages until you stop being able to tell which one you're looking at.

14:58 <_whitenotifier-c> [nmigen] rroohhh commented on issue #391: Weird simulation behaviour with clock's and Instances - https://git.io/JfrVL

15:00 <vup> Is something like a generic / vendor agnostic framework to generate clocks / describe clock relations something that is planned / in scope for nmigen down the line?

15:01 <vup> together with xdr = n for n > 2 support, that would make truly cross vendor fpga implementations for a wide range of designs possible I think

15:44 <ZirconiumX> nmigen-boards would also need more standardisation of naming though

16:18 <vup> ZirconiumX: in which regard? For standard interfaces than is very much the plan I think.

16:19 <ZirconiumX> Exactly that

16:22 <vup> Ah, I think the plan is to add more things like SDRAMResource as the design space gets known

16:25 <awygle_> I was wondering if I should drop a PR for a DDR2Resource and the like

16:37 <vup> I mean I would appreciate it

22:22 <whitequark> awygle: yeah certainly welcome! there's an open issue for that

22:39 <_whitenotifier-c> [nmigen] whitequark commented on issue #391: Weird simulation behaviour with clock's and Instances - https://git.io/Jfrd4

23:10 <_whitenotifier-c> [nmigen] rroohhh commented on issue #391: Weird simulation behaviour with clock's and Instances - https://git.io/JfrFk

23:19 <_whitenotifier-c> [nmigen] whitequark commented on issue #391: Weird simulation behaviour with clock's and Instances - https://git.io/JfrF0

23:19 <_whitenotifier-c> [nmigen] whitequark closed issue #391: Weird simulation behaviour with clock's and Instances - https://git.io/JfwiV

23:19 <_whitenotifier-c> [nmigen] whitequark commented on issue #391: Weird simulation behaviour with clock's and Instances - https://git.io/JfrFu

23:42 <_whitenotifier-c> [nmigen] rroohhh commented on issue #391: Weird simulation behaviour with clock's and Instances - https://git.io/JfrbR

23:44 <_whitenotifier-c> [nmigen] whitequark commented on issue #391: Weird simulation behaviour with clock's and Instances - https://git.io/Jfrbu

23:59 <_whitenotifier-c> [nmigen] rroohhh commented on issue #308: Support Platforms that include an existing design and expose interface to that design as Resource - https://git.io/JfrbX