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<awygle>
The best bit about the abc pdr engine is that it gives near minimal, relevant counterexample traces
<awygle>
No weird induction traces
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<_whitenotifier-9>
[nmigen] whitequark commented on issue #374: Bad error message when using Signal in add_clock_constraint not actually used in the design - https://git.io/Jf3BM
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<_whitenotifier-9>
[nmigen] whitequark commented on issue #374: Bad error message when using Signal in add_clock_constraint not actually used in the design - https://git.io/Jf3RE
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<whitequark>
so i just discovered how [get_ports foo[1]] works in vivado
<whitequark>
in spite of tcl using [ as a special character
<whitequark>
you can try and guess
<awygle>
Uh... A reader macro
<whitequark>
they made every integer a command that returns itself, bracketed, as a string
<awygle>
Or similar. An interception before the tcl layer
<awygle>
That is a good point which I could not even access through my disbelief
<awygle>
Oh this is like that ruby bare strings hack
<awygle>
That makes slightly more sense
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<daveshah>
#vivadotrivia it seems to accept arbitrary length (or at least very long) positive integers, but the largest negative integer it will accept is 2^32-1
<daveshah>
*-(2^32-1)
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<whitequark>
daveshah: why do you know this.
<daveshah>
I just tried it now
<daveshah>
I was curious about
<whitequark>
oh ok good. i was wondering about it too
<daveshah>
<sorear> there are _quite a few_ integers
<whitequark>
but assumed it doesn't support negative integers
<daveshah>
It even seems to support hex
<whitequark>
because why would you want negative bits in ports?
<daveshah>
pretty sure both Verilog and VHDL support them
<daveshah>
no idea why you'd want them though
<daveshah>
maybe for fixed point stuff
<daveshah>
and even if they aren't used for ports, I guess tcl is used for introspection and stuff too
<daveshah>
hmm, looks like Vivado's regexes are a bit loose
<daveshah>
Vivado% 0xcursed
<daveshah>
[0xcursed]
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<whitequark>
daveshah: do you recall if ISE prj files are tcl?
<daveshah>
Haven't used ISE for about 5 years so can't remember I'm afraid
<Sarayan>
vhdl work "../array920/FD9CE.vhd"
<Sarayan>
vhdl work "../array920/capture.vhd"
<Sarayan>
vhdl work "../array920/Tx_frame.vhd"
<Sarayan>
vhdl work "../array920/FD32CE.vhd"
<Sarayan>
(etc)
<Sarayan>
that's not very... anything, in fact
<whitequark>
it could be valid tcl
<Sarayan>
it does have a tcl interface
<Sarayan>
so... maybe?
<Sarayan>
(also, ISE 9.2i, which is not yet old enough to vote but close)
<Sarayan>
(2007)
<whitequark>
Sarayan: nope, not tcl, something custom
<_whitenotifier-9>
[nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±7] https://git.io/Jf3zu
<_whitenotifier-9>
[nmigen/nmigen] whitequark 6cee280 - plat, vendor: systematically escape net and file names in Tcl.
<_whitenotifier-9>
[nmigen] whitequark closed issue #375: Net names are not escaped properly for vivado tcl - https://git.io/JfO3L
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