ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen
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<awygle> oo, cool
<awygle> did we decide it was not possible to warn on a bare `signal.eq(value)` (i.e. one without an `m.d.sync +=`)?
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* zignig emerges from ISO, takes some photos... https://zignig.github.io/posts/powerlines/
* zignig continues programming.
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<_whitenotifier-c> [nmigen-soc] anuejn opened issue #15: more fine-grained memorymap - https://git.io/JfBtV
<_whitenotifier-c> [nmigen] anuejn opened issue #386: Inverted DiffPairs in connectors - https://git.io/JfBqK
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<vup> awygle: there was some discussion here: https://freenode.irclog.whitequark.org/nmigen/2020-04-23#26874731
<vup> tldr: would be nice, but is hard to do without false positives from nmigen internals
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<_whitenotifier-c> [nmigen] whitequark commented on issue #386: Inverted DiffPairs in connectors - https://git.io/JfBc1
<_whitenotifier-c> [nmigen-soc] whitequark commented on issue #15: more fine-grained memorymap - https://git.io/JfBcH
<_whitenotifier-c> [nmigen-soc] whitequark closed issue #15: more fine-grained memorymap - https://git.io/JfBtV
<_whitenotifier-c> [nmigen-soc] anuejn commented on issue #15: more fine-grained memorymap - https://git.io/JfBcj
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<_whitenotifier-c> [nmigen-boards] peteut synchronize pull request #49: Add Digilent Genesys2 board - https://git.io/JvgDS
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<awygle> is there some way to get pysim to regularly inform me its alive?
<awygle> mm i guess not
<awygle> if it's _dead_ dead it'll just die, if it's stuck it has no way of knowing that
<ZirconiumX> awygle: Since testsuites have a python script drive them, you can implement that inside your script
<awygle> mhm, that's what i'm doing
<awygle> hard to strike the right balance of "chatty" :p
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