<awygle>
Yosys is "Yosys open synthesis suite", this is just the parsers basically, "Yosys open parsing suite" gives "yopas"
<whitequark>
'just the parsers'?
<whitequark>
no no the "small" package stays nmigen-yosys
<awygle>
Isn't it like, RTLIL to verilog and CRTLIL to cxxrtl?
<whitequark>
the question is how the "full" package should be named
<awygle>
Ohhh I was confused.
<awygle>
Well in that case "portable open synthesis suite" gives you "posys" and "wasm open synthesis suite" gives you wosys which is nicely close to woesys
<awygle>
"python open synthesis suite" gives "pyosys" lol
<whitequark>
pyosys already exists
<whitequark>
that's the python yosys bindings it distributes
<whitequark>
and one of the reasons the new packages *have* to have a prefix / different name is to avoid confusion there
<awygle>
ah. bummer. Yosys has python bindings?
<whitequark>
since the wasm pypi packages will *not* export it
<whitequark>
yes.
<whitequark>
well.
<whitequark>
sort of
<awygle>
Lol
<whitequark>
you do *not* want to see how they work
<awygle>
You're usually right wq, I see no need to doubt you now
<awygle>
Well I brainstormed some, I'm out, time to go get a cheesecake
<cr1901_modern>
I like posys as a pun on another Portable and Open Systems Interface
<cr1901_modern>
... that's not what it stands for
<whitequark>
to be clear, it's not a different name for *yosys*
<whitequark>
because it should work for nextpnr, icestorm, and so on too
<cr1901_modern>
So it's "everything and the kitchen sink", so to speak
<whitequark>
yes
<cr1901_modern>
Maybe someone can make a good name out of that, but a prefix that encompasses "we include everything" would be good.
<awygle>
"whammyflow"
<awygle>
(i'm not helping)
<awygle>
"wif" - wasm integrated flow
<cr1901_modern>
waifu- WAsm Integrated Flow for Users
<awygle>
oh god
<awygle>
i was trying to be helpful, cr
<cr1901_modern>
uh huh...
* awygle
tries to make "ahegao" work...
<cr1901_modern>
Isn't that the hair antenn-
<cr1901_modern>
/me gets pulled off the stage by a hook
<awygle>
ngl i get those mixed up every time
<awygle>
thankfully it doesn't come up much but if i _do_ want to say "ahoge" i have to triple check it
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* whitequark
stares at awygle and cr1901_modern
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* hell__
quietly disappears inside a mess of computers and wires
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<_whitenotifier-f>
[nmigen/nmigen] whitequark pushed 2 commits to master [+0/-0/±2] https://git.io/JfQ6E
<_whitenotifier-f>
[nmigen/nmigen] whitequark 5f30bcb - back.cxxrtl: allow injecting black boxes.
<Sarayan>
flatten-hdlname is gone, what should I track?
<whitequark>
master
<Sarayan>
of you or of yosys main?
<Sarayan>
I want to play with some cxxrtl :-)
<Sarayan>
I need to do something fun and easy
<whitequark>
of yosys
<Sarayan>
everything is upstream? way cool
<whitequark>
yea
<Sarayan>
fwiw, quartus internals are an horribly inefficient mess
<whitequark>
news at 11
<Sarayan>
heh
<Sarayan>
oh, question. If I create multiple domains through EnableInserter/DomainRenamer, can I be allowed to have the same signal set in multiple domains, is there a way to tell nmigen their phase signals are never active at the same time or set a priority or something?
<Lofty>
Hi Sarayan
<Sarayan>
Hi Lofty
<Sarayan>
Wanna be called Lofty, ZX or whatev'?
<Lofty>
Lofty is fine, although Zirc and ZX still highlight me :P
* Lofty
just added ZirconiumX to the list
<whitequark>
Sarayan: a signal is driven from exactly one domain
<hell__>
otherwise, you have Problems
<whitequark>
no
<whitequark>
you just can't drive a signal from multiple domains in nmigen
<whitequark>
even in cases where it wouldn't be problematic
<hell__>
it would not synthesize then, I guess
<hell__>
(or you can't even write it using the allowed syntax)
<whitequark>
latter
<hell__>
good
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<Sarayan>
so it's a case when you still have to write the with m.If
<Sarayan>
hopefully that's not needed often
<hell__>
if possible, I'd use simple logic gates
<Sarayan>
not sure what that means
<Lofty>
That's what m.If translates into, most of the time
<Lofty>
Also, Sarayan, I pinged you a bunch in Mistral :P
* hell__
really needs to bridge the gap between hardware and firmware
<whitequark>
*all of the time, since you can't get a latch from m.If
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<kbeckmann>
is it possible to end up with latches with nmigen? i have only managed to get latches when doing something very wrong in verilog, and as i understand it latches should be avoided like the plague.
<Lofty>
kbeckmann: no, it isn't
<kbeckmann>
awesome
<Lofty>
Or at least, not without direct instantiation :P
<kbeckmann>
ah yes, that's something i wouldn't do unless i knew what i was doing (which i don't)
<Lofty>
But yes, latches *should* be avoided like the plague...on FPGAs, at least
<Lofty>
On ASICs they need less area
<Lofty>
But managing latches is kind of a nightmare
<kbeckmann>
i see. the world of asics seems very far away for me though. wonder when we'll be able to do low cost / shared wafers oshpark-style :)
<Sarayan>
A latch is something that can change state anything the clock is high instead of just when the clock rises, right?
<Lofty>
Yeah, it has an enable input
<Lofty>
If the enable is high it passes output through
<Lofty>
If it's low, it holds state
<Sarayan>
yeah, in static nmos is a pair of crossed inverters, in dynamic nmos it's just a mosfet letting the signal thought
<Sarayan>
through
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<kbeckmann>
whitequark: i have assembled a pergola board for you now, can post it your way if you privmsg or dm your shipping details.
<cr1901_modern>
Did nmigen ever depend on jsonschema at any time? I have a copy floating around on a remote machine, and I've no idea why I downloaded it
<cr1901_modern>
But guessing I was testing something w/ it
<cr1901_modern>
hmmm, nope!
<Sarayan>
Warning: Design contains buffered combinatorial wires, which require delta cycles during evaluation.
<Sarayan>
I'm not sure what it means exactly
<Lofty>
Sarayan: "your design will be unnecessarily slow to simulate"
<Sarayan>
That I got
<cr1901_modern>
Delta cycles is a VHDL thing that nmigen adopted. Last time I tried understanding them, I quit in frustration.
<Sarayan>
The part I don't is what I did wrong in the design
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<whitequark>
cr1901_modern: Verilog has delta cycles too
<whitequark>
<= introduces a delta cycle
<whitequark>
really, any kind of serial simualtor for a parallel language will have delta cycles under one name or another