01:21 <cr1901_modern> whitequark: https://insights.sigasi.com/opinion/jan/vhdls-crown-jewel/ I probably misunderstood this article then. It opens with "VHDL’s delta cycle algorithm in action". Made me think it's a VHDL thing.l

01:23 <whitequark> VHDL uses different delta cycles than Verilog

01:24 <whitequark> but both of them use delta cycles in the same technical sense

01:24 <whitequark> what differs is the way they resolve race conditions

02:10 <whitequark> kbeckmann: lemme dm re: pergola

07:03 <Sarayan> How do I write to a single-wire debug_item? And where should I read from?

07:43 <whitequark> read from .curr, write to .next

07:52 <Sarayan> thanks, found the info in the capi header

07:53 <Sarayan> I should change signals when clk is 0 or 1?

07:54 <Sarayan> I'm never sure

08:01 <Sarayan> oh sad, I can't copy-construct a debug_item

08:01 <Sarayan> oh well

08:12 <Sarayan> yay, nothing works, but since the code is reasonably easy to read I should be able to debug it :-)

08:12 <Sarayan> fairly certain it's all my fault

08:14 <Sarayan> ok, I'm fucking up the EnableInserter and friends

08:16 <whitequark> why do you need to copy-construct a debug_item?

08:16 <whitequark> regarding changing signals: you should not do it at the same time that your logic runs

08:16 <whitequark> i.e. if your logic runs at posedge, you have two step() calls

08:16 <whitequark> one does clk 0->1, another clk 1->0

08:16 <whitequark> you need to change inputs at the second call

08:16 <Sarayan> ok, so when clock is 1

08:17 <Sarayan> I'm doing pure nmigen without specifying, so that means posedge, right?

08:18 <whitequark> yes

08:18 <Sarayan> good, it's intuitive

08:20 <Sarayan> Are EnableInserter/DomainRenamer documented somewhere? I probably have some stupid syntax error

08:21 <Sarayan> and I'd like to stop annoying you all the time

08:28 <Sarayan> fwiw https://github.com/galibert/retrofpga/tree/master/m68000 is what I'm trying with the domains in m68000.py and most of their use in gen.py. The generated c++ code shows the nclk domain doesn't really exist

08:28 <Sarayan> only pclk

08:28 <Sarayan> s/gen.py/eclock.py/

08:28 <Sarayan> corry

08:30 <Sarayan> as for the copy-construct, I was thinking about having global objects (not pointers) for the main signals like the clocks and the phases. So it's not copy-construct either, sorry I'm kinda tired, it's default constructor and operator =

08:31 <Sarayan> it removes one indirect access

09:12 <Sarayan> ok, the domains are working and I'm dumb, weee

10:01 <Sarayan> yay it works

10:01 <Sarayan> As expected, I was stupid, not nmigen :-)

13:19 <Sarayan> I'm looking for a design recommendation: I have some instruction decode PLAs that take a 16-bits instruction and gives out a 10-bit microcode address. They're nand/nor in design, and mostly run on the 16 bits and their negations, with sometimes some other lines procomputed (like is it a 32 bits instruction). How should I write that?

13:19 <Sarayan> roughly 50 matches each time

13:38 <Lofty> I'd consider a Memory for that, using the init value as a ROM

13:38 <whitequark> yep

13:42 <Sarayan> Three 65536x10 memories?

13:42 <Sarayan> that's a lot

13:42 <Lofty> What's the name for the ".template" part of C++ "a.template blah<foo>()" syntax?

13:43 <Lofty> Where you need to use the template keyword to get it to compile

13:43 <Sarayan> you need more than the template keyword though

13:43 <Sarayan> it's typename you tend to have to sprinkle around

13:44 <Lofty> Here it's very specifically template

13:45 <whitequark> Lofty: https://en.cppreference.com/w/cpp/language/dependent_name

13:46 <Sarayan> https://og.kervella.org/m68k/schem/

13:46 <whitequark> https://stackoverflow.com/questions/7923369/when-is-the-typename-keyword-necessary

13:46 <Sarayan> youcan see the two of them at the bottom, the bottomest one generates one 10-bits address, the one on top of it two more

13:47 <Lofty> Thank you, whitequark

15:58 <whitequark> awygle: name idea for the wasm toolchain: "Wasp"

15:58 <whitequark> Web Assembly Synthesis Package

16:33 <ktemkin> accompanied by HORNET, the Horribly Overengineerined Runtime for Netlist Elaboration and Translation

16:34 <ktemkin> s/Runtime/Redistributable, if you like

16:34 <whitequark> that's vtr right

16:35 <ktemkin> lol, it definitely fits vtr

16:40 <whitequark> in general, do y'all find the project useful?

16:44 <ktemkin> the wasm toolchain?

16:44 <Sarayan> the wasm toolchain or nmigen in general?

17:48 <awygle> "wasp" is pretty good

17:55 <awygle> i like the project a lot

17:55 <awygle> idk how much i'm personally gonna use it, but i could see it being great for e.g. glasgow

17:58 <kbeckmann> i can see it being very useful during workshops where peple show up without any preparation at all and can start generating bitstreams almost immediately.

17:59 <anuejn> yup

17:59 <awygle> mhm

17:59 <awygle> plus i like it just like... philosophically

17:59 <anuejn> also for really having a web toolchain it might be quite handy

18:00 <kbeckmann> yeah, tie it together with webusb and you can deploy your bitstream on a board too

18:00 <awygle> not enough projects provide "slow and portable" and "fast and native" as _options_ instead of just picking one

18:00 <awygle> and this seems like a good way to do that without doubling your overheads

18:07 <smkz> mayb prepend something like "unitary" or "unified" to the name to make it clear that it's All The Stuff packed into one package; also "UWASP" is a lot easier to disambiguate vs a common English word when searching etc

18:46 <awygle> micro-wasp

19:02 <agg> It seems like a really nice enabler for even higher level projects like ktemkin's sdr idea where I imagine requiring your sdr users have yosys master and nextpnr installed on the system is a pretty big jump over just python

21:00 <ktemkin> it's definitely going to be nice for stuff like USB-analyzer-hardware-triggering; and maybe next-generation-facedancer, where asking users to install a whole toolchain is non-ideal

21:09 <Sarayan> if I do a Cat(self.i_ird, self.l, self.bw) in a switch, and a m.Case('----------011----1'), should it match on ird == 0x61 ?

21:10 <Sarayan> maybe what I'm asking is cat is the bit order on a Cat

21:12 <Sarayan> ah, found the answer

21:12 <Sarayan> the other way around than what I expected