ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at
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<Sarayan> wq: thanks
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<Sarayan> Damn the optimization is aggressive
<Sarayan> every signal not routed externally or used in computing an externally routed signal is dropped
<Sarayan> which means if you want to debug a submodule you have to route it out
<daveshah> you can prevent this by using the keep attribute on signals
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<jeanthom> Hi, as a follow-up to #406 I tried to use BB and that partially fixed my problems
<jeanthom> Its OE signal is generated by a TSHX2DQA which requires to be connected to a top level tristate
<whitequark> Sarayan: you can also use -Og with CXXRTL
<whitequark> jeanthom: hm, I see
<daveshah> jeanthom: important to note that ECP5 does not have an "output enable" signal like iCE40s but a "tristate" signal that is the inverse logic
<daveshah> (Xilinx also uses a "tristate" type signal)
<whitequark> jeanthom: either you'll have to actually control all the signals at once, or you'll have to manually instantiate all those in the toplevel module
<whitequark> so it's probably time to figure out whether you can control all of them at once.
<daveshah> I don't know about Diamond, but nextpnr currently does not duplicate TSHX2DQAs so you will need to instantiate them per pin
<daveshah> Even if it could duplicate them, you would need one per 8 pins not one for the whole 16 pins as the DQSW270 signal is only for an 8-bit DQS group
<jeanthom> mmh so LiteDRAM ECP5 PHy could be simplified a bit?
<daveshah> I would rather not go to the hassle of duplicating them, I doubt that Diamond duplicates them anyway
<jeanthom> it instantiates a TSHX2DQA for every DQ and DQS pin
<daveshah> duplicating them in nextpnr
<daveshah> If you can confirm that Diamond does support duplicating them, then I can implement that in nextpnr
<jeanthom> whitequark, What would be the best way to declare the DQ/DQS pins for a DDR3 chip in the platform file? Assuming that you want to have direction control for each bank (not each pin in the bank)
<jeanthom> You'd have a Subsignal for each bank?
<jeanthom> s/bank/8-bit group/, not sure if it should be called a bank
<whitequark> yes
<whitequark> something like dq0 dq1 dq2 dq3 etc
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<shizoor> Apologies, the firewall booted me. I'm trying to read from a memory for a VGA output and the build time is massive.
<agg> total shot in the dark but as a very quick thing to try, you could put transparent=False on the read_port() call if you're not already
<shizoor> Ah right, there is no read_port() call. It's a "Memory" object from nmigen_soc.memory.
<shizoor> videomem = Memory( width = 9, depth = 158730,
<shizoor> init = ( 0x000000 for i in range( 158730 ) ) )
<agg> how do you read from it without making a read port?
<agg> also that's... very deep, what fpga are you using?
<shizoor> m.d.sync+=vgapins.x.eq(videomem[self.v_timer])
<shizoor> LatticeICE40
<shizoor> I'm probably doing it completely wrong.
<agg> yea :p
<agg> so, two things first
<agg> you need to create a read_port by calling read_port() on the memory object and add that to your submodules list, then it has an addr and data attribute for setting address and reading data
<agg> second, your fpga probably doesn't have that much memory
<agg> you're asking for 174kB
<shizoor> Yeah, a screen of VGA at 9 bits.
<agg> which ice40 are you using, exactly? e.g. up5k or hx8k?
<shizoor> 3 bits for red, green and blue.
<shizoor> hx8k
<agg> so it has a total of 128kbits of embedded memory
<agg> you're asking for 1395kbits
<shizoor> Ah. That'd sort of rain on my parade.
<agg> yea...
<agg> if you want a full frame buffer for full vga, you'll need some sort of external memory and an interface to it
<agg> usually what people would do is a lower resolution vga, or smaller colour depth, or generate it on the fly from a smaller underlying representation
<shizoor> Yeah, I've been doing horrible blocky graphics.
<agg> what board is your fpga on?
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<shizoor> Sorry again, the firewall doesn't like me talking outside China. I'll have missed the reply.
<agg> I just asked what board your fpga is on, in case it already has some external memory you could use
<whitequark> shizoor: can you access the irc logs?
<shizoor> Yes.
<whitequark> you can use those to look for replies! the logger even has a live mode
<shizoor> I remember you saying something about a register but couldn't find it.
<shizoor> Cool, yes, I'll search that for other people having the same issue.
<agg> sorry, I mean "what PCB is it on" / what FPGA development board you're using
<agg> probably the easiest thing to do for now is to use a much smaller memory though, interfacing with external memory is a reasonable complexity jump
<whitequark> shizoor: oh I meant only that you can use it to see what people replied to you when the firewall kicks you out
<shizoor> HX8K breakout board, then wired manually to a iCE40-IO
<whitequark> that wasn't implying that you didn't search enough or something, sorry if it came out like that
<shizoor> You're too nice :)
<shizoor> Bing works out here, and I can sometimes get on VPN. I'll grab some other examples of where people have read / write from memory and keep it small.
<shizoor> They block github a lot though. I don't understand the rationale behind that at all.
<Lofty> Software that lets you circumvent the GFW I'd imagine
<shizoor> Lol, mine is OpenVPN and an Asus router on the floor in my front room back in Wales.
<shizoor> I've got a route set up to my static on my cable modem here in China, I terminal server onto a box in my house, use it to change mac, my housemate then can't get the internet so reboots the cable modem and it comes back on a different IP address. Can't believe they haven't cottoned onto blocking by DNS hostname.
<shizoor> Thanks again all. :)
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