05:33 <Sarayan> wq: thanks

09:08 <Sarayan> Damn the optimization is aggressive

09:09 <Sarayan> every signal not routed externally or used in computing an externally routed signal is dropped

09:09 <Sarayan> which means if you want to debug a submodule you have to route it out

09:10 <daveshah> you can prevent this by using the keep attribute on signals

12:01 <jeanthom> Hi, as a follow-up to #406 I tried to use BB and that partially fixed my problems

12:01 <jeanthom> Its OE signal is generated by a TSHX2DQA which requires to be connected to a top level tristate

12:05 <whitequark> Sarayan: you can also use -Og with CXXRTL

12:05 <whitequark> jeanthom: hm, I see

12:06 <daveshah> jeanthom: important to note that ECP5 does not have an "output enable" signal like iCE40s but a "tristate" signal that is the inverse logic

12:06 <daveshah> (Xilinx also uses a "tristate" type signal)

12:06 <whitequark> jeanthom: either you'll have to actually control all the signals at once, or you'll have to manually instantiate all those in the toplevel module

12:06 <whitequark> so it's probably time to figure out whether you can control all of them at once.

12:09 <daveshah> I don't know about Diamond, but nextpnr currently does not duplicate TSHX2DQAs so you will need to instantiate them per pin

12:09 <daveshah> Even if it could duplicate them, you would need one per 8 pins not one for the whole 16 pins as the DQSW270 signal is only for an 8-bit DQS group

12:11 <jeanthom> mmh so LiteDRAM ECP5 PHy could be simplified a bit?

12:11 <daveshah> I would rather not go to the hassle of duplicating them, I doubt that Diamond duplicates them anyway

12:11 <jeanthom> it instantiates a TSHX2DQA for every DQ and DQS pin

12:12 <daveshah> duplicating them in nextpnr

12:12 <daveshah> If you can confirm that Diamond does support duplicating them, then I can implement that in nextpnr

12:59 <jeanthom> whitequark, What would be the best way to declare the DQ/DQS pins for a DDR3 chip in the platform file? Assuming that you want to have direction control for each bank (not each pin in the bank)

13:00 <jeanthom> You'd have a Subsignal for each bank?

13:00 <jeanthom> s/bank/8-bit group/, not sure if it should be called a bank

13:03 <whitequark> yes

13:03 <whitequark> something like dq0 dq1 dq2 dq3 etc

14:26 <shizoor> Apologies, the firewall booted me. I'm trying to read from a memory for a VGA output and the build time is massive.

14:28 <agg> total shot in the dark but as a very quick thing to try, you could put transparent=False on the read_port() call if you're not already

14:29 <shizoor> Ah right, there is no read_port() call. It's a "Memory" object from nmigen_soc.memory.

14:29 <shizoor> videomem = Memory( width = 9, depth = 158730,

14:29 <shizoor> init = ( 0x000000 for i in range( 158730 ) ) )

14:29 <agg> how do you read from it without making a read port?

14:30 <agg> also that's... very deep, what fpga are you using?

14:30 <shizoor> m.d.sync+=vgapins.x.eq(videomem[self.v_timer])

14:30 <shizoor> LatticeICE40

14:30 <shizoor> I'm probably doing it completely wrong.

14:30 <agg> yea :p

14:30 <agg> so, two things first

14:31 <agg> you need to create a read_port by calling read_port() on the memory object and add that to your submodules list, then it has an addr and data attribute for setting address and reading data

14:31 <agg> second, your fpga probably doesn't have that much memory

14:31 <agg> you're asking for 174kB

14:32 <shizoor> Yeah, a screen of VGA at 9 bits.

14:32 <agg> which ice40 are you using, exactly? e.g. up5k or hx8k?

14:32 <shizoor> 3 bits for red, green and blue.

14:32 <shizoor> hx8k

14:33 <agg> so it has a total of 128kbits of embedded memory

14:33 <agg> you're asking for 1395kbits

14:33 <shizoor> Ah. That'd sort of rain on my parade.

14:33 <agg> yea...

14:33 <agg> if you want a full frame buffer for full vga, you'll need some sort of external memory and an interface to it

14:33 <agg> usually what people would do is a lower resolution vga, or smaller colour depth, or generate it on the fly from a smaller underlying representation

14:34 <shizoor> Yeah, I've been doing horrible blocky graphics.

14:34 <agg> what board is your fpga on?

14:37 <shizoor> Sorry again, the firewall doesn't like me talking outside China. I'll have missed the reply.

14:37 <agg> I just asked what board your fpga is on, in case it already has some external memory you could use

14:37 <whitequark> shizoor: can you access the irc logs?

14:37 <shizoor> Yes.

14:38 <whitequark> you can use those to look for replies! the logger even has a live mode

14:38 <shizoor> I remember you saying something about a register but couldn't find it.

14:38 <shizoor> Cool, yes, I'll search that for other people having the same issue.

14:39 <agg> sorry, I mean "what PCB is it on" / what FPGA development board you're using

14:39 <agg> probably the easiest thing to do for now is to use a much smaller memory though, interfacing with external memory is a reasonable complexity jump

14:39 <whitequark> shizoor: oh I meant only that you can use it to see what people replied to you when the firewall kicks you out

14:40 <shizoor> HX8K breakout board, then wired manually to a iCE40-IO

14:40 <whitequark> that wasn't implying that you didn't search enough or something, sorry if it came out like that

14:40 <shizoor> You're too nice :)

14:42 <shizoor> Bing works out here, and I can sometimes get on VPN. I'll grab some other examples of where people have read / write from memory and keep it small.

14:44 <shizoor> They block github a lot though. I don't understand the rationale behind that at all.

14:45 <Lofty> Software that lets you circumvent the GFW I'd imagine

14:46 <shizoor> Lol, mine is OpenVPN and an Asus router on the floor in my front room back in Wales.

14:47 <shizoor> I've got a route set up to my static on my cable modem here in China, I terminal server onto a box in my house, use it to change mac, my housemate then can't get the internet so reboots the cable modem and it comes back on a different IP address. Can't believe they haven't cottoned onto blocking by DNS hostname.

14:52 <shizoor> Thanks again all. :)