ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at · IRC meetings each 1st & 3rd Monday at 1800 UTC · next meeting July 20th
<whitequark> wow, this is a massive amount of scrollback
<DaKnig> sorry... I had quite a lot of trouble getting everything to work.
<whitequark> no problem at all
<whitequark> i'm just internally debating whether i should stop reading it all heh
<DaKnig> miek: I saw a similar example before, but what I dont understand is this: it calls `.request("led")` but in my platform file I cant find the string "led" anywhere
<DaKnig> is that something internal to the `LEDResrources` class?
<DaKnig> how can I specify which LED specifically I want to be used for this?
<whitequark> yes, it's interrnal to LEDResources (which is just a function)
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<DaKnig> how can I tell it which LED I want it to choose?
<DaKnig> can I do someting like "led[3]"?
<miek> .request("led", 3)
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<Yehowshua> Does anyone know how to use DomainRenamer()?
<Yehowshua> I had used it a long time ago here -> , but I don't think I did it quite right
<Yehowshua> Please forgive that code - its pretty awful overall
<Yehowshua> I'm trying to rename a domain in a submodule
<miek> it's renaming the clock domain, not the clock signal. so, "sync" to something else
<miek> you'll also need to create the ClockDomain that you rename to. here's an example:
<Yehowshua> oh! that makes sense now
<Yehowshua> Thanks
<miek> also, DomainRenamer("radio") there is a shortcut for DomainRenamer({"sync": "radio"})
<whitequark> i'm wondering how much sense would it be to explain domain renaming in terms of variable bindings in the manual
<whitequark> one time i tried making an analogy it fell completely flat
* miek googles "variable bindings" :p
<whitequark> oh, right, that might be part of the problem
<whitequark> i think about variable bindings all the time but most people might not have a mental model of them nearly as clear/explicit
<_whitenotifier-b> [nmigen-boards] whitequark closed pull request #83: mercury: fix SPI roles -
<_whitenotifier-b> [nmigen/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-b> [nmigen/nmigen-boards] rroohhh d9264bf - mercury: fix SPI roles
<Yehowshua> What's really been helpful is learning by example
<Yehowshua> soft documentation I guess its called
<whitequark> yeah, examples definitely are necessary and will be the primary way people learn
<whitequark> i mean, we're going to have a proper tutorial
<whitequark> and some cheatsheet pages
<Yehowshua> From a sophomore student's perspective, that is good.
<Yehowshua> At my school, Python is now required instead of Matlab, I think it nMigen should be fairly accesible
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<d1b2> <emeb> As a long-time Matlab user I think this is a good thing.
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<d1b2> <TiltMeSenpai> so Kate's LUNA platform uses d_p/d_m for usb data lines, but it looks like the nmigen-boards platforms use d_p/d_n for the data lines. Would it be appropriate to make a PR to one of the projects so nmigen-boards platforms could work nicer with LUNA's gateware and/or where would that belong?
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<Yehowshua> d1b2, do you have some code already? nMigen boards for TinyFPGABX at least has usb_p and usb_n
<Yehowshua> I have a working example of UART on USB with nMigen too
<d1b2> <TiltMeSenpai> oh does the irc show the user as d1b2
<Yehowshua> Also, ktemkin, thanks for the example yesterday. I've made yet another example of AyncFifo with producer -> consumer
<Yehowshua> You nick is db12, your name is TiltMeSenpai...
<Yehowshua> No. actually is says `1BitSquared Discord Bridge`
<d1b2> <TiltMeSenpai> ah, I'm on the Discord side of the bridge, my name here is TiltMeSenpai. Anyways, I'm messing around with the Orangecrab, I managed to get the usb serial example from LUNA working on it but it involved changing more things than I'd prefer
<Yehowshua> d1b2, that's fantastic
<Yehowshua> I just lookedd up orangecrab
<Yehowshua> Wow - didn't even know about it - I wish there was an official ECP5 list
<Yehowshua> Is the orange crab in production?
<d1b2> <TiltMeSenpai> yeah you can either buy them from 1bitsquared's store or the groupgets store
<d1b2> <TiltMeSenpai> lemme look up the links
<Yehowshua> Nice. Lemme snag one
<Yehowshua> d1b2, also, you mentioned free node nMigen has a Discord bridge?
<d1b2> <TiltMeSenpai> yeah, I'm on the 1bitsquared Discord server, there's a bot that syncs messages from the nmigen channel here to the nmigen freenode channel
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* awygle declares scrollback bankruptcy
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<lkcl> awygle: lol. likewise. i had to use the irc logs yesterday. hexchat's scrollback buffer wasn't long enough
<lkcl> DaKnig: i encountered the exact same type of thing when installing vivado a couple of years ago. as i "know vaguely what i am doing" from 20 years messing with GNU/Linux OSes, i "solved" the problem of things like having different names by creating symlinks in /usr/lib.
<lkcl> ln -s /usr/lib/libftdi{VERSIONTHATCENTOSINSTALLED} /usr/lib/libftdi{NAMETHATVIDADOEXPECTS}.so
<lkcl> however for that to work you **MUST** know that the versions - major and minor - are the same.
<lkcl> if they are not, then yes you are stuck with the situation of basically having to build your own OS.
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<Yehowshua> jeanthom, is gram ddr3 working?
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<whitequark> you can just package libftdi of the version it expects and use LD_LIBRARY_PATH
<whitequark> you don't need to rebuild the whole thing
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<DaKnig> is this a known issue?
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<Yehowshua> What tool is that from? That doesn't look like an nMigen issue...
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<DaKnig> vivado doesnt like the primitives nmigen uses for something
<Lofty> It shouldn't be difficult to fix
<FL4SHK> is there any way I can output 156 MHz signals to a DAC for VGA output?
<FL4SHK> 156 MHz was what I needed for 1080p
<Lofty> FL4SHK: are you trying to drive VGA and HDMI with the same clock?
<FL4SHK> no, just VGA
<Lofty> 156MHz pixel clock is really high
<Lofty> Hmmm
<FL4SHK> yes, but it's what I need for 1080p VGA
<Lofty> Anyway, why can't you output 156MHz signals?
<FL4SHK> I'm concerned about signal integrity
<Lofty> ...How so?
<FL4SHK> because 156 MHz signals have all these high frequencies
<Lofty> That's mostly for the PCB
<Lofty> From an FPGA point of view, sure, you can output 156MHz signals
<FL4SHK> the signal is exiting the FPGA
<FL4SHK> so it needs to deal with signal integrity
<Lofty> That's on your PCB
<FL4SHK> my concern is that the thing won't work even if the FPGA code is completely verified as working
<daveshah> VGA at worst will be a bit blurry if the SI is wrong
<Lofty> Then maybe have a chat with awygle or somebody who knows how to do high-frequency PCB work
<FL4SHK> I see
<daveshah> In theory, terrible quality on the hsync/vsync could cause the monitor not to sync, but I've done some pretty ropey things and it's run fine even at 1080p
<daveshah> the other thing to do is start at 640x480 (~25MHz pixel clock), which also makes timing closure easier
<daveshah> and then try intermediate resolutions and look to see if there is any degradation going up
<FL4SHK> Well, I've got 25 MHz signals generated just fine
<FL4SHK> one of my projects is going to just output a 640 by 480 resolution
<FL4SHK> another will be using the 1080p resolution
<FL4SHK> I should probably just focus on one project
<FL4SHK> the two things will be using two different dev boards anyway
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<d1b2> <נמר הגוקו> What are the boolean AND, OR equivalents that I can use for If blocks at migen? can I use the python 'and', 'or'?
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<Yehowshua> I believe you have to use ampersand
<Yehowshua> and pip
<Yehowshua> **pipe
<Yehowshua> In general, you can experiment with the nMigen language live in the REPL
<Yehowshua> for example:
<Yehowshua> You can play in the REPL that way
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<Yehowshua> Just re-read your question. Inside `m.If():`, you can do `m.If(a &b):` where `a` and `b` are both signals
<Yehowshua> `m.If(a & b):`
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<DaKnig> 156MHz is not that high for some digital things
<awygle> 156 MHz isn't too fast. Easy to make work with minimal precautions
<FL4SHK> I see
<DaKnig> FL4SHK dont be concerned about the frequencies. my board is ok with outputting 400MHz digital signal
<FL4SHK> DaKnig: here's a thing you can do: translate the nMigen code into Verilog, then use Verilog tools
<FL4SHK> I see
<FL4SHK> I'll have to give it a shot, then
<DaKnig> if you are working with VHDL or Verilog you just use the right buffer primitive and it just works. dont worry about signal integrity, it was the manufacturer's job.
<DaKnig> one thing to keep in mind though is the cable
<DaKnig> long cable or just cheap cable might ruin the signal
<FL4SHK> I don't use primitives
<FL4SHK> it's not portable
<DaKnig> with analog you would just get worse picture quality which is not a big deal
<DaKnig> with digital, like HDMI, it might lose pixels and just stop working
<DaKnig> VGA doesnt really need much care on your side- worst case you get a blurry pic, but that's not that bad... its ok as long as the control signals are ok
<DaKnig> and you got the timing right
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<Yehowshua> Yeah. Many analog monitors are pretty forgiving. That's a pic of a MacSE when I tried to drive it with an FPGA 1KHz off
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<daknig2> is there any reference for using hdmi stuff with nMigen? or at least for how to use differential pairs? I have an onboard hdmi port which is defined as a few tmds ports (and other stuff) in the platform file, and I need to use them
<awygle> Define the pins with DiffPairs
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<_whitenotifier-b> [nmigen-boards] DaKnig opened issue #84: wrong type of buffer primitive used in series 7 -
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