<_whitenotifier-b>
[nextpnr] whitequark created branch update-deps - https://git.io/JJY7T
<_whitenotifier-b>
[nextpnr] whitequark opened pull request #3: Auto-update - https://git.io/JJY7k
<mithro>
whitequark: I've sometimes pondered if there could be some useful auto-generated documentation coming from the board definitions too...
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<whitequark>
mithro: yep, we can do that too perhaps...
<whitequark>
i'd need to collaborate with someone on that
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<awygle>
wow, i just wrote `def Foo(Elaboratable)` instead of `class Foo(Elaboratable)`
<awygle>
i should go to bed
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<awygle>
i want to be mad at python for not exploding but i think actually even rust might have been cool with this
<zignig>
awygle: tee hee, try prolog instead.
<awygle>
prolog is cool
* zignig
likes when code gets to the point where the infrastructure built, makes bigger things easier.
<zignig>
awygle: prolog is cool for __some__ problems.
<awygle>
sure, i wouldn't try to write most things in it
<awygle>
idk how useful it is to me
<awygle>
but it's cool :p
<zignig>
I nearly have a working command console on my boneless SOC. ASM clicked again last week and it suddenly got much easier.
<awygle>
nice!
<awygle>
i can refresh DDR2 now :p
* awygle
zzz
<zignig>
sweet! , isn't it more fun to wait for the values to degrade and get RRAM ?
<zignig>
awygle: or is that you falling asleep at the terminal (again ;P) ?
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<MadHacker>
Can some kind soul help me with how DomainRenamer works? I'm trying to use LUNA's USB stuff in a design where sync is not the normal 48MHz clock; from playing about LUNA only seems to work if sync is my clk48 though. As a test case I've actually stripped out sync entirely, so I can tell if anything tries to use it. I'm doing m.submodules.usb=DomainRenamer("clk48")(USBSerialDevice(blah)) but it still
<MadHacker>
seems to be trying to access the parent's nonexistent sync CD.
<MadHacker>
I tried {"clk48":"sync"} and vice-versa too. Miss out the USB bits and my code indeed builds fine with no sync domain present at all.
<MadHacker>
Changing sync to be the clk48 and LUNA works fine too, just the rest of my design doesn't work in that domain. :)
<agg>
MadHacker: have you made a new ClockDomain from your clk48 signal and added it to m.domains?
<MadHacker>
Yes.
<agg>
And then something like m.submdoules.luna = DomainRenamer("clk48cd")(luna) ?
<MadHacker>
To be clear, I've stripped out *all* use of sync, and that builds fine minus the USB bits. With the USB bits present, it works with m.d.comb += [ClockSignal("sync").eq(ClockSignal("clk48")]
<agg>
(fwiw you don't need the square brackets, you can add single statements)
<MadHacker>
Yes agg. Literally the line I said, m.submodules.usb=DomainRenamer("clk48")(USBSerialDevice(blah))
<MadHacker>
Aware, I habitually put them in because there's good odds I'm going to add things. :)
<agg>
Looks ok... maybe post a snippet with the whole cd setup?
<MadHacker>
I have code that doesn't use sync (provably; adding in a use of sync makes it protest about sync not being defined). I try to use a DomainRenamer to rename luna to also not use sync. No joy.
<MadHacker>
It's not a generic clock domain setup issue. It's a domain renamer thing.
<agg>
What error/behaviour do you get?
<MadHacker>
With USB commented out: No error. With USB present using that renamer to avoid the use of "sync", nmigen.hdl.cd.DomainError: Domain 'sync' is used but not defined
<MadHacker>
If I create a sync domain and tie it to my clk48, it works fine - but I don't want to do that, I want to use sync for another completely unrelated domain everywhere else.
<MadHacker>
Here, stripped back to almost minimum: https://pastebin.com/Q7mxmBJD - builds fine, uncomment m.submodules.usb = usb and it won't.
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<_whitenotifier-b>
[nmigen] GuzTech commented on issue #425: Support for PLL primitives - https://git.io/JJOvc
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<MadHacker>
Oh dear.
<MadHacker>
I found out what's up.
<MadHacker>
It's sync being used from Rose() and Past() in LUNA.
<MadHacker>
ktemkin: LUNA's yours, yes? I think those Rose() and Past() bits might need tweaked if you have a non-USB-related system-wide sync.
<MadHacker>
I had to tweak them in receiver.py and endpoint.py to coax it into working for me. :/
<MadHacker>
whitequark: I take back all of what I said and now regrettably admit that Rose/Fell/Past have unfortunate footgun tendencies.
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<TD-Linux>
one other way to solve the virtual power problem is have nmigen platforms be able to elaborate logic, and then assign the pins so anything else would be a multiple assignment
<TD-Linux>
elaborating logic would also allow me to implement bootloader reset functionality with orangecrab's button in the platform
<daveshah>
The ULX3S has/had something with connecting a button to the ESP32 iirc
<TD-Linux>
I never soldered the esp32 on to mine. I should try it
<MadHacker>
ktemkin: I've submitted a pull request for changing those rose/fell bits. Works On My Machine(TM). :)
<FL4SHK>
so it looks like I need to build an AST of sorts
<FL4SHK>
just for expressions
<FL4SHK>
also, I think I'll pull an nMigen for scopes
<FL4SHK>
or, well, pull a `with`
<FL4SHK>
currently thinking of supporting unnamed scopes for labels
<FL4SHK>
I've done this before in my more stereotypical assemblers
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<_whitenotifier-b>
[YoWASP/nextpnr] whitequark pushed 1 commit to update-deps [+0/-0/±2] https://git.io/JJOUa
<_whitenotifier-b>
[nextpnr] whitequark opened pull request #4: Auto-update - https://git.io/JJOcg
<_whitenotifier-b>
[nextpnr] whitequark created branch update-deps - https://git.io/JJY7T
<ktemkin>
MadHacker: just catching up now
<ktemkin>
thanks for trying that out and poking around
<ktemkin>
if you get rid of the changes adding domain=“sync” instance of Rose/Fell, I’d gladly merge the rest of the PR :)
<ktemkin>
*to instances of
<ktemkin>
so, basically: skipping the SPI code section
<agg>
ktemkin: I think the sync ones are the problem in that case, i.e. if you use Rose/Fell/Past with domain=None (default), it gets turned in to "sync" _after_ renaming, so can't be renamed, so incorrectly uses the sync domain when every other use of sync has been changed
<agg>
(or, well, the cause is probably more complicated and I'm basically guessing at why it happens exactly)
<agg>
whitequark: I looked a bit more, probably telling you what you already know but the Rose/Fell etc make a Sample(domain=None), the None is only changed to "sync" by the SampleDomainInjector in Module.elaborate()
<agg>
and as far as I can tell at that point it's too late for the DomainRenamer to see it
<whitequark>
yep
<whitequark>
that whole part of design was a mistake
<agg>
so I can see why setting domain="sync" when creating the Rose/Fell etc fixes the immediate issue