04:59 <tannewt> anyone have experience getting diamond going with nmigen on arch linux? pnmainc exits with code 255 for me

05:10 <cr1901_modern> tannewt: _Possibly_ relevant: https://github.com/nmigen/nmigen/pull/410#issuecomment-647472577

05:11 <tannewt> thanks!

05:13 <tannewt> ooooh, I get output now

05:13 <cr1901_modern> Setting up diamond properly is kinda garbage IMO

05:14 <tannewt> yuuuuup. that's why I'm willing to help with the open tools

08:52 <ktemkin> for reference, Arch is where I run Diamond; both with nMigen and otherwise

08:53 <ktemkin> it works out of the box as long as you have the right environment file source’ing

08:53 <ktemkin> I can help with that when I’m awake if you run into more troubles

09:50 <zignig_> ktemkin: I finally have luna_acm and a boneless running at 12Mhz on my tinybx.

09:51 <zignig_> just the echo for now, not hooked together. That is next.

11:18 <tucanae47_> hello guys, i have been trying to put together an example of wishbone bridge like https://github.com/im-tomu/fomu-workshop/blob/master/litex/workshop_rgb.py#L37 in the fomu workshop(i want to do the same without a soc cpu), im trying to learn how to use wishbone with nmigen, but almost everything is wrriten inside soc libraries and im having a hard time to understand, i tried to isolate the wishbone bus funcaionality

11:18 <tucanae47_> with using a core from fomu-workshop here https://trinket.io/python/4ab7de47af but im doing something wrong and i think i dont need csr for this, but is hard to isolate for me. any hints, tips?

11:19 <tucanae47_> hello guys, i have been trying to put together an example of wishbone bridge like https://github.com/im-tomu/fomu-workshop/blob/master/litex/workshop_rgb.py#L37 in the fomu workshop(i want to do the same without a soc cpu), im trying to learn how to use wishbone with nmigen, but almost everything is wrriten inside soc libraries and im having a hard time to understand, i tried to isolate the wishbone bus funcionality

11:19 <tucanae47_> here https://trinket.io/python/4ab7de47af but im doing something wrong and i think i dont need csr for this, but is hard to isolate for me. any hints, tips?

11:19 <tucanae47_> (sorry for duplicated msg)

11:23 <zignig> tucanae47_: mifune has been looking at that, https://twitter.com/mifune/status/1289954784988954630

11:48 <tucanae47_> thanks thats helpful, from that seems luna seems also an option, havent tried it yet, wondering if that setup works with https://github.com/litex-hub/wishbone-utils/tree/master/wishbone-tool

11:48 <tucanae47_> that setup i mean https://twitter.com/ktemkin/status/1280991512289931265

11:49 <jeanthom> tucanae47_, https://github.com/jeanthom/gram/blob/master/examples/uartbridge.py I have a UART <-> Wishbone bridge that works with wishbone-tool

11:49 <jeanthom> I never tried LUNA's CDC-ACM though

11:51 <tucanae47_> @jeanthom thanks! will try :)

12:11 <d1b2> <286Tech> Is there a way to create 2D arrays of signals? I have a list of signals, but I cannot index it with a signal.

12:12 <zignig> d1b2: how did you want that back ? the selected signal in a single register ?

12:18 <d1b2> <286Tech> Ah, apparently an Array type exists for this purpose.

12:23 <zignig> https://github.com/RobertBaruch/nmigen-tutorial/blob/master/6_combining.md#arrays

13:25 <zignig> slowing the core down to 12Mhz has blown out zignigs bootloader sequence.

13:36 <zignig> time.sleep FTW !

13:36 <zignig> and a longer fifo.

13:41 <d1b2> <286Tech> Hmm, I'm getting an assertion error assert defs[sig] is self in ir.py, but I don't quite understand why.

13:41 <d1b2> <286Tech> I'm just connecting some signals to some outputs.

13:42 <d1b2> <286Tech> If I comment out the part where I connect signals to OLED pins, then there's no error.

13:45 <vup> @286Tech that happens when there is a direction mismatch somewhere, maybe the OLED pins have the wrong directron in the board file or something like that

13:46 <vup> *direction

13:46 <d1b2> <286Tech> Yeah, that could be. Let me double check

13:47 <d1b2> <286Tech> Yup, I forgot to add dir="o" to the Pins.

13:47 <d1b2> <286Tech> Thank you 🙂

15:01 <tannewt> ktemkin: I got it working if I switched from pnmainc to diamondc. I don't have any environment variables. I just copied the license to the default path

18:21 <whitequark> would be an interesting compiler

18:21 <tannewt> :-)

18:50 <ktemkin> pandemicc sounds like it’s a frontend for about half of many languages

18:51 <whitequark> mhm

18:51 <ktemkin> or a multi-FPGA HLS engine that targets being able to compile half of the C standard

19:09 <tpw_rules> ktemkin: augh

19:26 <tannewt> ktemkin: what is in your diamond environment file?

19:53 <d1b2> <Chips4Makers> @Kate Temkin: that HLS engine is called BAMBU

20:04 <whitequark> tannewt: export NMIGEN_ENV_Diamond=/usr/local/diamond/3.10_x64/bin/lin64/diamond_env

20:04 <whitequark> this should've been in the docs but it seems i forgot to put it in

20:05 <tannewt> 👍

20:05 <whitequark> (adjust for your version/bitness accordingly)

20:05 <tannewt> thanks!

20:25 <cr1901_modern> whitequark: This does not work for Windows (when changing the paths appropriately); there is no diamond_env.bat. I point to this script instead:

20:25 <cr1901_modern> @echo off

20:25 <cr1901_modern> set PATH=C:\lscc\diamond\3.11_x64\bin\nt64;%PATH%

20:26 <cr1901_modern> Which works fine. Worth putting in the docs?

20:26 <cr1901_modern> Or is this "you're on your own power-user" territory?

21:04 <d1b2> <286Tech> Aaaaaand I've ported the ULX3S OLED example to nMigen as well: https://twitter.com/BitlogIT/status/1293654444803072000

21:05 <d1b2> <286Tech> The OLED connector is also not in the ULX3S platform file. I'll create a PR for that too.

21:11 <_whitenotifier-3> [nmigen-boards] GuzTech opened pull request #104: Add OLED connector to ulx3s.py - https://git.io/JJ9Ex