ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting August 3rd
_whitelogger has joined #nmigen
Degi has quit [Ping timeout: 264 seconds]
Degi has joined #nmigen
emeb has quit [Ping timeout: 264 seconds]
emeb has joined #nmigen
emeb has quit [Ping timeout: 264 seconds]
emeb has joined #nmigen
<_whitenotifier-b> [nmigen-boards] ktemkin reviewed pull request #95 commit - https://git.io/JJoql
<_whitenotifier-b> [nmigen-boards] ktemkin synchronize pull request #95: resources: allow use of ULPI PHYs with active-low RST pins - https://git.io/JJgUB
<_whitenotifier-b> [nmigen-boards] ktemkin commented on pull request #95: resources: allow use of ULPI PHYs with active-low RST pins - https://git.io/JJoq2
jaseg has quit [Ping timeout: 260 seconds]
jaseg has joined #nmigen
<_whitenotifier-b> [nmigen-boards] ktemkin synchronize pull request #94: Add HADBadge (Hackaday Supercon Badge). - https://git.io/JJucq
<_whitenotifier-b> [nmigen-boards] ktemkin reviewed pull request #94 commit - https://git.io/JJoYM
electronic_eel has quit [Ping timeout: 256 seconds]
electronic_eel has joined #nmigen
PyroPeter_ has joined #nmigen
PyroPeter has quit [Ping timeout: 265 seconds]
PyroPeter_ is now known as PyroPeter
emeb has left #nmigen [#nmigen]
d1b2 has quit [Remote host closed the connection]
d1b2 has joined #nmigen
_whitelogger has joined #nmigen
jeanthom has joined #nmigen
hitomi2507 has joined #nmigen
jeanthom has quit [Ping timeout: 246 seconds]
proteus-guy has joined #nmigen
Asu has joined #nmigen
chipmuenk has joined #nmigen
jeanthom has joined #nmigen
jeanthom has quit [Remote host closed the connection]
jeanthom has joined #nmigen
jjeanthom has joined #nmigen
jeanthom has quit [Read error: Connection reset by peer]
noknok has joined #nmigen
jjeanthom has quit [Ping timeout: 240 seconds]
<DaKnig> in m.If statements, what should I use for logical operators?
<DaKnig> for things like `if a==1 and b==2:`
<agg> (a==1) & (b==2)
<DaKnig> `and` just checks if the expressions are equal to None right?
<DaKnig> and this check is not delayed or something
<agg> `and` is python's logical AND operation, but it happens at python-time and does not create an nmigen expression
<agg> (because a Signal can't override it, iirc, it always converts its arguments to bools)
<DaKnig> aha, its a bit strange that you cant override this
<agg> whereas `&` is a bitwise operator in python (but note its different precedence), and Signal gets to define how that's handled, so it can create an nmigen expression
<agg> be sure to have those brackets otherwise you'll be evaluating a == (1 & b) == 2
<agg> the problem is that in python, `and`/`or` are guaranteed short-circuiting, so they have to immediately convert their arguments to bools
<agg> there was a proposal to allow overriding that (https://www.python.org/dev/peps/pep-0335/) but it got rejected
jjeanthom has joined #nmigen
noknok has quit [Ping timeout: 256 seconds]
noknok has joined #nmigen
jjeanthom has quit [Ping timeout: 246 seconds]
<DaKnig> would have been nice to be able to overload all operators like in C++
<DaKnig> ok thanks
jeanthom has joined #nmigen
noknok has quit [Ping timeout: 256 seconds]
<DaKnig> one thing I did not find there - would this code: `with m.If(a):` behave as expected when len(a)>1?
<lkcl_> agg: it does seem particularly odd that int, float and all other objects have overrides __xor__, __ge__, etc. etc. yet bool does not have __and__ __or__ and __not__
<DaKnig> wdym
<DaKnig> you can do both `True&True` and `True and True`
<lkcl_> DaKnig: yes - this is a nmigen workaround, by overloading the bitwise "&" operator
<DaKnig> lkcl_:
<lkcl_> overloading the bitwise *python* "&" operator
<lkcl_> not overloading the *boolean* python operator... because you can't.
<lkcl_> oink.
<lkcl_> dir(bool) shows that it does actually have __or__, __and__, __xor__ etc. which is *really* obtuse and plain weird.
<whitequark> lkcl_: bool is a subclass of int, in python
<whitequark> (mostly because python always had ints but it didn't always have bools)
<lkcl_> whitequark: intriguing. last time i read the c code of python extensively it was 2.1 which was... 19 years ago now?
<DaKnig> LOL
<DaKnig> whats new in python 2.3
<whitequark> >Python's Booleans were not added for the sake of strict type-checking. A very strict language such as Pascal would also prevent you performing arithmetic with Booleans, and would require that the expression in an if statement always evaluate to a Boolean result. Python is not this strict and never will be, as PEP 285 explicitly says.
<lkcl_> in 2006-2007 i was working for NATO Research: the delay and cost in Military "approval" processes meant that they were still using python 2.1 :)
* lkcl_ is having to do migen FSMs for litex simulation
<lkcl_> urr....
<lkcl_> interestingly though there is the concept of "NextValue" in migen FSMs
<lkcl_> urrr in migen if you accidentally mix comb and sync (by not using NextValue) you get *silent* failure, no warnings
<lkcl_> whitequark: i am just... really relieved that you know what you're doing.
<DaKnig> `a=Signal(10); a.cast(5)` doesnt behave as I expected
<whitequark> lkcl_: yeah, that's why you regularly write rants on the libresoc bugtracker all but accusing me of incompetence
<whitequark> DaKnig: unfortunately, that's how python class methods work
<whitequark> i'm not aware of any reasonable way to warn on that
<lkcl_> whitequark: that's an unfortunate misperception / misunderstanding / misreading, i can only apologise for
<lkcl_> at some point we'll both feel comfortable - and safe - being able to discuss this and get to the bottom of it, properly.
<lkcl_> oh: do remember to fill in the NLNet Request for Payment, and let me know when you've emailed it to them?
<whitequark> already done a few days ago
<lkcl_> ah good. i did ask if you could let me know that you'd done it so i can mark the records as "done".
<lkcl_> updated. they should take... 2 weeks? if you need it sooner ping me ok?
<whitequark> 2 weeks is fine
<lkcl_> fantastic. debugging cxxsim and fixing that issue that cesar tracked down we can also easily justify putting in some more EUR for you.
<DaKnig> `Value.any` is the same as `Value.bool`, right?
<whitequark> yes
zignig has joined #nmigen
<zignig> ping!
<jeanthom> hi zignig
<zignig> jeanthom: hey !
<zignig> what faboulus thing are you building in nmignen ATM ?!
<jeanthom> I'm working on https://github.com/jeanthom/gram
<FL4SHK> I'm trying to build a GNU Binutils port for my custom processor
<zignig> I think I have that starred...
<FL4SHK> which I plan to use inside of a game console
<FL4SHK> er, for the assembler for a game console
<zignig> I have a banner on a sythetic CPU with an echo console.
<zignig> unce unce unce
<FL4SHK> I don't completely know what I'm doing with Binutils
<FL4SHK> I found it easier to mess with GCC
* zignig need less BEER.
<FL4SHK> I actually got a GCC port working for one of my CPUs once
<FL4SHK> but I verified it by examining the assembly output of g++
<FL4SHK> it was fun making that
<zignig> FL4SHK: how goes you asm builder ?
<FL4SHK> currently? I don't know
<FL4SHK> I'm having to examine existing Binutils ports
<FL4SHK> because the documentation doesn't handle everything...
<zignig> are you making a C target ?
<FL4SHK> a C target?
<FL4SHK> I do plan on making GCC target this machine.
* zignig is making a compiler !C python constructs only.
<FL4SHK> ...oh yeah, if anyone here knows how to make Binutils ports, I could use some advice
<zignig> what is this COMPUTER thing that you speak of? BORK
* zignig should not IRC in this state. GNITE ALL!
* zignig ZZZ
* zignig hails battery powered clippers. no hairyness for youl
<miek> clipper usage may be a bad idea in this state, too :p
<zignig> too late , 0.2 mm cranium , beard to be determined/
<hell__> i could use some of that
<zignig> you need to beware of the cold, ... BRAIN FREEZE if you are not careful
<zignig> .au is getting warme, so OK
<zignig> ran out of batteries , luckily all good.
proteus-guy has quit [Ping timeout: 246 seconds]
chipmuenk1 has joined #nmigen
chipmuenk has quit [Ping timeout: 244 seconds]
chipmuenk1 is now known as chipmuenk
emeb has joined #nmigen
<_whitenotifier-b> [nmigen] jeanthom opened pull request #465: nmigen.sim._pyrtl: Add support for Assert - https://git.io/JJK3H
<jeanthom> Should we implement Assume like an assertion
<jeanthom> or just ignore it in pysim?
<daveshah> Convention in simulation is to treat it like an assertion
<daveshah> iirc there is another keyword for assume but ignored in simulation, I think it is "restrict"
<FL4SHK> I have yet to do nMigen simulation...
<FL4SHK> I've done just formal verification and testing on a real FPGA
<FL4SHK> :P
<_whitenotifier-b> [nmigen] jeanthom commented on pull request #465: nmigen.sim._pyrtl: Add support for Assert - https://git.io/JJKsB
<_whitenotifier-b> [nmigen] rroohhh opened pull request #466: vendor.lattice_machxo_2_3l: add SRAM svf generation - https://git.io/JJKs6
<_whitenotifier-b> [nmigen] rroohhh edited pull request #466: vendor.lattice_machxo_2_3l: add SRAM svf generation - https://git.io/JJKs6
<_whitenotifier-b> [nmigen] jeanthom synchronize pull request #465: nmigen.sim._pyrtl: Add support for Assert - https://git.io/JJK3H
<_whitenotifier-b> [nmigen] jeanthom synchronize pull request #465: nmigen.sim._pyrtl: Add support for Assert - https://git.io/JJK3H
<DaKnig> I cant find a way to cast a value to another shape, does nmigen not have this?
<DaKnig> I have an 8bit value that I want to 0 extend (or sign extend, doesnt matter)
<DaKnig> I mean, for sign extend I can always do `C(0,4) - x` to sign extend it to 4 bits but...
<jeanthom> daveshah, Any idea on how we should handle Cover in simulation?
<_whitenotifier-b> [nmigen] jeanthom edited pull request #465: nmigen.sim._pyrtl: Add support for Assert/Assume - https://git.io/JJK3H
<Lofty> DaKnig: that's what issue #464 is about
<daveshah> jeanthom: probably ignore them, unless you want to use them for actual coverage analysis
<Lofty> DaKnig: you can try the `x | C(0, 4)` trick
FFY00 has quit [Ping timeout: 260 seconds]
FFY00 has joined #nmigen
lkcl_ has quit [Ping timeout: 246 seconds]
lkcl_ has joined #nmigen
emeb has quit [Read error: Connection reset by peer]
emeb1 has joined #nmigen
emeb1 has quit [Client Quit]
emeb has joined #nmigen
jeanthom has quit [Ping timeout: 260 seconds]
hitomi2507 has quit [Quit: Nettalk6 - www.ntalk.de]
jeanthom has joined #nmigen
jeanthom has quit [Ping timeout: 264 seconds]
Kekskruemel has joined #nmigen
<_whitenotifier-b> [nmigen-boards] rroohhh opened pull request #97: Add TE0714-03-50-2l - https://git.io/JJK0Z
<emeb> happy to see #464 discussion. I just came up against this in some of my own code this morning and just used an intermediate signal for clarity.
<_whitenotifier-b> [nmigen-boards] rroohhh opened pull request #98: CI: install wheel manually - https://git.io/JJKuG
<awygle> emeb: plz comment on issue w/ opinions :D
<emeb> awygle: I'll try. Just a bit reticent due to inexperience :)
jeanthom has joined #nmigen
<lkcl_> DaKnig: https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/extend.py;hb=HEAD
<lkcl_> DaKnig: truncate is trivial. x.eq(y[:new_length])
Kekskruemel has quit [Remote host closed the connection]
<_whitenotifier-b> [nmigen] emeb commented on issue #464: [RFC] Shape Conversion Operators Round 2 - https://git.io/JJK28
cr1901_modern has quit [Read error: Connection reset by peer]
cr1901_modern has joined #nmigen
Asuu has joined #nmigen
Asu has quit [Ping timeout: 246 seconds]
<_whitenotifier-b> [nmigen] whitequark commented on issue #464: [RFC] Shape Conversion Operators Round 2 - https://git.io/JJKaY
<_whitenotifier-b> [nmigen-boards] whitequark commented on pull request #98: CI: install wheel manually - https://git.io/JJKaG
<_whitenotifier-b> [nmigen/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JJKaZ
<_whitenotifier-b> [nmigen/nmigen-boards] rroohhh 8de6100 - CI: install wheel manually
<_whitenotifier-b> [nmigen-boards] whitequark closed pull request #98: CI: install wheel manually - https://git.io/JJKuG
<_whitenotifier-b> [nmigen] emeb commented on issue #464: [RFC] Shape Conversion Operators Round 2 - https://git.io/JJKaP
<_whitenotifier-b> [nmigen] whitequark commented on issue #464: [RFC] Shape Conversion Operators Round 2 - https://git.io/JJKVT
<_whitenotifier-b> [nmigen] awygle commented on issue #464: [RFC] Shape Conversion Operators Round 2 - https://git.io/JJKVQ
chipmuenk has quit [Quit: chipmuenk]
<DaKnig> lkcl_: yeah thanks. I like the trick with the |C(0,width)
Asuu has quit [Quit: Konversation terminated!]
<lkcl_> DaKnig: o yeah, i really should have done that as Const(0, fullwidth-width) rather than use Repl, however you can see i must have cut/paste exts() to create extz().
<_whitenotifier-b> [nmigen] awygle commented on issue #464: [RFC] Shape Conversion Operators Round 2 - https://git.io/JJKoK
<_whitenotifier-b> [nmigen] whitequark commented on pull request #466: vendor.lattice_machxo_2_3l: add SRAM svf generation - https://git.io/JJKob
emeb has quit [Quit: Leaving.]
<_whitenotifier-b> [nmigen] rroohhh synchronize pull request #466: vendor.lattice_machxo_2_3l: add SRAM svf generation - https://git.io/JJKs6
<_whitenotifier-b> [nmigen] rroohhh commented on pull request #466: vendor.lattice_machxo_2_3l: add SRAM svf generation - https://git.io/JJK6a
<_whitenotifier-b> [nmigen] rroohhh edited a comment on pull request #466: vendor.lattice_machxo_2_3l: add SRAM svf generation - https://git.io/JJK6a
lkcl_ has quit [*.net *.split]
DaKnig has quit [*.net *.split]
trabucayre has quit [*.net *.split]
anuejn has quit [*.net *.split]
agg has quit [*.net *.split]
lkcl_ has joined #nmigen
DaKnig has joined #nmigen
anuejn has joined #nmigen
agg has joined #nmigen
trabucayre has joined #nmigen
<_whitenotifier-b> [nmigen] adamgreig commented on issue #464: [RFC] Shape Conversion Operators Round 2 - https://git.io/JJKiP