ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at · IRC meetings each Monday at 1800 UTC · next meeting August 17th
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<whitequark> awygle: think you could guide GuzTech in nmigen-boards#103,#104?
<whitequark> i think we already have examples of those resources somewhere in other boards, and #103/#104 should be consistent with those
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<tannewt> what is `defparam` in verilog and how does it map to nmigen? I'm looking at the nmigen EFB
<d1b2> <edbordin> defparam lets you parametrize your design (e.g. you could make data width a parameter). in nmigen you can just pass parameters into the constructor for your module class
<d1b2> <edbordin> looks like defparam might also be used to define constants sometimes
<d1b2> <edbordin> oh but maybe you were asking how to set those params from nmigen if importing some verilog. that I don't know
<tannewt> ah! I see I can do `p_` as a kwarg for it to be snagged as a parameter by Instance
<d1b2> <edbordin> ah, nice one
<tannewt> this should help me fuzz the EFB :-)
<d1b2> <edbordin> ooh, fuzzing with nmigen, nice idea
<d1b2> <TiltMeSenpai> I'm just saying
<d1b2> <TiltMeSenpai> you might be able to use this to make a generalized nmigen-based fuzzing thing
<d1b2> <edbordin> I'm not sure how similar to software fuzzing it is
<d1b2> <edbordin> I guess you could use it to automatically figure out what configurations are valid for each block rather than setting those enumerations/range up yourself
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* zignig was chasing the wrong ghost, PLL takes time to settle.
<zignig> not 16->12Mhz
<_whitenotifier-3> [nmigen/nmigen] whitequark pushed 1 commit to master [+1/-0/±0]
<_whitenotifier-3> [nmigen/nmigen] whitequark f6f9d68 - Add Linguist tags to .gitattributes.
<_whitenotifier-3> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13]
<_whitenotifier-3> [nmigen/nmigen] whitequark 7e8e66e - Deploying to gh-pages from @ f6f9d68f24ee19b52f115dd6b8012b5f395d537f 🚀
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<pepijndevos> heh... so the nMigen repo mentions #m-labs as the place to be, but... there is also this channel?
<whitequark> i don't think it does, pepijndevos
<whitequark> as you can probably see by commit dates there, m-labs is no longer involved with development
<pepijndevos> I seeee... that explains... a lot
<pepijndevos> glad to be here at least :)))
<pepijndevos> So in typical fashion my "hello world" is a very atypical thing that immediately dumps me in sparsely documented edges of nMigen haha
<whitequark> what kind of thing is it?
<pepijndevos> Basically I want to add a fixed point number type that correctly propagates the number of fractional bits and all that
<whitequark> (nmigen is generally sparsely documented; that's something i consider a priority)
<whitequark> hmm
<pepijndevos> so I'm currently going over
<whitequark> if you're thinking of inheriting from the nmigen AST classes: this isn't supported in general
<pepijndevos> I figured I could just subclass signal and overwrite some operators haha
<pepijndevos> But yea, seems like it's a bit more tricky
<whitequark> nope, that's something i specifically do not support and reserve the right to break between releases
<whitequark> what you can do, though, is to inherit from... well
<pepijndevos> right... this line made me think I might be on the wrong path
<pepijndevos> UserValue seems to be... made for subclassing, but I don't think that immediately lets me do what I want.
<whitequark> yup
<whitequark> the thing about nmigen is that it's even lower-level than verilog or vhdl. you don't even really have types; there are "shapes", which are similar to extremely weak types, but don't fulfill quite the same role
<whitequark> it's a toolkit for constructing RTL netlists. it specifically leaves high-level concepts like types, in the usual sense, out of scope. there's some plumbing for enumerations, but those are still just integers after all
<pepijndevos> But a shape does track things like signedness. Basically I want a custom shape that also tracks fractional bits.
<whitequark> you can't do that
<pepijndevos> hmhm...
<whitequark> and like i mentioned, it's out of scope, very much on purpose
<whitequark> shapes provide the bare minimum necessary for synthesis (you need width and signedness to synthesize arithmetics, especially considering DSP inference) and verification (you need enums to have readable VCDs and such)
<pepijndevos> So what would be the way to do it? Just implement my own *actual* type that implements all the operations and methods to convert to and from nMigen types?
<whitequark> are you familiar with basics of LLVM IR?
<pepijndevos> Not really.
<whitequark> right, nevermind then
<whitequark> (what would be the way to do it) yes, pretty much. it depends on your precise goals, really
<whitequark> for example, i would suggest you consider building the entire numeric tower on top of nmigen, including integers
<whitequark> i.e. don't even allow bare nmigen values as operands
<pepijndevos> right
<whitequark> nmigen is a language you can use directly, sure, but it is also a compiler-as-a-library that something HLS-y can target as a backend
<pepijndevos> Yea, I'm sortof writing a compiler
<whitequark> (i use a somewhat unorthodox definition of "HLS", which is basically "everything more complex than RTL". Verilog is HLS :)
<pepijndevos> hehe ok
<whitequark> or let me rephrase it in a different way
<whitequark> you might think of nmigen as a convenient way to construct RTLIL
<pepijndevos> definitely... actually...
<whitequark> this isn't true in the strictest sense (it's not tied to RTLIL, and it doesn't map 1:1 to RTLIL), but there's a philosophical truth in that statement
<pepijndevos> What I have not thought through is, if I use my own number types... at some point I need to roundtrip my values through comb/sync and it seems I'd basically have to strip all type info.
<whitequark> can you describe a specific example of a problem you're anticipating?
<pepijndevos> ah... hmmm, actually maybe it's fine?? I'd basically just implement eq() to return the assignment of the underlying signal, while my code just uses my own types
<whitequark> yup
<pepijndevos> whew... okay I think I'm getting there. as I said... not a typical "hello world" experience haha
<whitequark> so... the thing about UserValue is that it leaks methods into your namespace, which is a major backwards compatibility hazard
<whitequark> we've redesigned it just a few weeks ago to fix that, with a much better design
<pepijndevos> huh?
<whitequark> well, UserValue inherits from Value, so unless you *un*define them, you'll get all the normal methods that apply to nMigen values, which you probably don't want
<whitequark> I made that mistake many months ago, when introducing it
<anuejn> pepijndevos: i have done something similiar to what you want and also went for the route to not subclass UserValue
<whitequark> tbh, you might not even need to subclass UserValue at all
<whitequark> yup, anuejn's approach is very sensible
<pepijndevos> yea, not planning on using uservalue
<whitequark> only drop down to nMigen values in .eq()
<whitequark> (the manual i'm writing currently should eventually gain a section on that)
<pepijndevos> anuejn, ohhh I might borrow some of that :))
<anuejn> :)
<anuejn> maybe we could even try to turn this into a proper library if there is interest
<anuejn> (and fix some mistakes / make it more generally useful)
<whitequark> sounds great to me, i think any exploration in that direction is valuable
<daveshah> +1, I'm unlikely to have time to use it any time soon but I like the idea of libraries providing HLS-esque features on top of nMigen
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<pepijndevos> anuejn, uh... what kind of mistakes generalizations?
<pepijndevos> Other than that, yea sound good
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<pepijndevos> Maybe I'm not getting it
<anuejn> the fixed point types are just always signed
<pepijndevos> ah ok
<pepijndevos> I'm writing my own type now that supports unsigned, hopefully...
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<pepijndevos> awwww, indices being backwards from VHDL/Verilog hurts my brain
<pepijndevos> bits_after_point: Value = self.value[:self.fmt.bits_after_point]
<pepijndevos> So bit 0 is LSB right?
<tpw_rules> yes
<pepijndevos> oof, crisis averted... casting to and from float and between different sizes seems to work
<lkcl> pepijndevos: consider yourself lucky you are not also implementing POWER9, which uses IBM MSB0 byte-ordering, urr....
<pepijndevos> considered :|
<lkcl> :)
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<DaKnig> pepijndevos: actually VHDL can have indices go both directions :)
<pepijndevos> Yea I know, but... convention is to not screw with my brain haha
<DaKnig> pepijndevos: why'd you want the other way around? maybe we can do something about that :)
<DaKnig> if you want the VHDL `a<="1010"` you can do `a.eq(0b1010)`
<pepijndevos> anuejn, why do you use a one-sided cast here rather than make both sides equivalent as in other operators?
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<anuejn> pepijndevos: that seems to be a bug
<anuejn> but mul is in fact a bit different than addition in fixed point math
<pepijndevos> yeah...
<pepijndevos> Just not 100% sure in which ways
<anuejn> because the bits before the point and after the point are each the sum of the corresponding operands bits
<pepijndevos> Yea, but is it valid to do assymetric multiplicatons?
<anuejn> so casting the second operand to the same type as the first one is definitely wrong (because of clamping and precision loss)
<anuejn> yup it perfectly is (according to wikipedia)
<anuejn> so the thing i wanted to do here was getting _some_ fixed point value
<anuejn> and then i was not very concentrated
<anuejn> but the problem when we have static floats as an input is: how do we decide on the format in which we want to represent them
<pepijndevos> Yea, I decide to just not support arbitrary numbers as operands, only my own type
<pepijndevos> Do you have this wikipedia link?
<anuejn> that is quite reasonable
<anuejn> the german wikipedia has this in a somewhat easier to understand way but it is in german :(
<pepijndevos> yea I cannot find anything about multiplication that is useful
<anuejn> that seems to do it :)
<anuejn> section "Calculating with fixed point numbers"
<pepijndevos> I'll just read the german lol
<pepijndevos> ... some time at least... good night :)
<anuejn> good night :)
<d1b2> <286Tech> Fixed-point multiplication of let's say [III.FFFF] x [II.FFFFFF] = [IIIII.FFFFFFFFFF]. That is 3 integer bits and 4 fractional bits times 2 integer bits and 6 fractional bits gives you a 5 integer, 10 fractional bit answer.
<d1b2> <286Tech> I use it in my fixed-point FFT implementations for my research.
<d1b2> <286Tech> So a Q8.8 multiplication with give a Q16.16 result. If you want to go back to a Q8.8 format, you'd have to truncate the upper 8 bits, and the lower 8 bits (or perform rounding).
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