<lkcl_>
no, it's being deprecated with something that's Record-like, based i think on a new class called UserValue which is under development
<moony>
something I often see with external devices is a bus that can be driven from either end, but that doesn't seem synthesizable, I guess those are never used internally?
<lkcl_>
mmmm... driven from both ends... mmm... ok it's "doable" by using a "shared write" system, as if it's a global bus
<lkcl_>
1 sec brb
<lkcl_>
back
<whitequark>
there are no internal tristates in FPGAs anymore
<moony>
makes sense, really, it's only really useful externally
<lkcl_>
so you _have_ to do a write-bus and a read-bus?
<whitequark>
they used to exist actually
<whitequark>
there are some FPGAs (and CPLDs) where you can even make an internal short
<lkcl_>
that doesn't sound good :)
<whitequark>
nowadays I believe there are only unidirectional buffers used mostly because that means your fanout isn't limited by capacitance
<moony>
it'd save some space to be able to use a tri-state bus, but it has it's risks and issues so I see why it's not a big thing
<DaKnig>
so have to double the number of wires going around the board
<DaKnig>
?
<moony>
DaKnig: IO can be tri-state
<moony>
as it's p much manditory to support that
<moony>
not doing so would render the FPGA incompatible with something as basic as SRAM
<DaKnig>
I mean inside the FPGA
<DaKnig>
from what I see one of the main factors in delay is wiring delay. more wires means it'd be harder for the p&^r stage, more silicon and more delay, no?
<whitequark>
DaKnig: it's not as straightforward
<whitequark>
remember that if you have internal tristates, your routing is done with pass transistors, and each time you turn one of those on, capacitance grows
<whitequark>
more capacitance means more delay, too
<whitequark>
also, more wires usually makes p&r's job easier
<DaKnig>
ah! I didnt think about the pass transistors.
<whitequark>
since it means that a less optimal routing solution can still actually fit into the device
<whitequark>
i remember daveshah telling me that the less confident a company is in their tooling, the more wires their FPGAs have
<whitequark>
eg ice40 has a lot more wires than 7-series, per logic element
<DaKnig>
but arent FPGAs designed to have small blocks of logic with *some* interconnect with other blocks (and a few layers of that down)? so you are limited by the interconnect allowed by each block?
<Sarayan>
well, altera/intel must have been very frightened of their tooling :-)
<Lofty>
Sarayan: you'll hear no complaints from me :P
<Sarayan>
even the blocks of logic are in large part routing
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<_whitenotifier-3>
[nmigen/nmigen-soc] jfng pushed 1 commit to master [+0/-0/±3] https://git.io/JJh6L
<_whitenotifier-3>
[nmigen/nmigen-soc] jfng ecfad4d - Clarify documentation for alignment parameters to mention it is log2.
<_whitenotifier-3>
[nmigen-soc] jfng closed issue #6: Clarify documentation for alignment parameters to mention that it is log2 - https://git.io/JvZvM
<whitequark>
Sarayan: didn't they start with vpr?
<Sarayan>
vpr?
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<Lofty>
It's still in Quartus
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<DaKnig>
can somebody give an example of simple instantiation of the PLL blocks in a 7-series device in nmigen?
<DaKnig>
I want to simply generate 2 frequencies from one given frequency, that would be phase locked and all that. I hear that I might be using primitives wrong, I'd like to see somebody else's example for that.
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