ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at · IRC meetings each Monday at 1800 UTC · next meeting August 17th
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<_whitenotifier-3> [YoWASP/yosys] github-actions[bot] pushed 1 commit to update-deps [+0/-0/±1]
<_whitenotifier-3> [YoWASP/yosys] github-actions[bot] dffa999 - Update upstream code
<_whitenotifier-3> [yosys] github-actions[bot] created branch update-deps -
<_whitenotifier-3> [yosys] github-actions[bot] opened pull request #13: Auto-update -
<tannewt> cr1901_modern: you around? I'm trying to tweak your bitstream parsing code to save into a bytearray or bytes rather than a large int
<cr1901_modern> tannewt: Busy I'm afraid
<tannewt> kk np
<_whitenotifier-3> [YoWASP/nextpnr] github-actions[bot] pushed 1 commit to update-deps [+0/-0/±1]
<_whitenotifier-3> [YoWASP/nextpnr] github-actions[bot] e0b8654 - Update upstream code
<_whitenotifier-3> [nextpnr] github-actions[bot] opened pull request #8: Auto-update -
<_whitenotifier-3> [nextpnr] github-actions[bot] created branch update-deps -
<_whitenotifier-3> [nextpnr] whitequark closed pull request #8: Auto-update -
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<_whitenotifier-3> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1]
<_whitenotifier-3> [YoWASP/nextpnr] github-actions[bot] 5385082 - Update upstream code
<_whitenotifier-3> [YoWASP/nextpnr] whitequark deleted branch update-deps
<_whitenotifier-3> [yosys] whitequark closed pull request #13: Auto-update -
<_whitenotifier-3> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1]
<_whitenotifier-3> [YoWASP/yosys] github-actions[bot] 7017d1c - Update upstream code
<_whitenotifier-3> [YoWASP/yosys] whitequark deleted branch update-deps
<_whitenotifier-3> [yosys] whitequark deleted branch update-deps -
<tannewt> how would I change an nmigen-board so it always instantiates and clocks the embedded function block so that it stays programmable over i2c?
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<whitequark> you can't do this at the moment
<whitequark> but it's a fairly often requested feature
<tannewt> kk, np. thanks!
<tannewt> I'll have a test harness sort of class anyway
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* zignig finally gets a working shell console.
<zignig> on <enter> , led goes on ; off <enter> led goes off. yay!
<d1b2> <TiltMeSenpai> 🎉
<zignig> TiltMeSenpai: thanks :)
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<pepijndevos> d1b2, TiltMeSenpai half-band filters can avoid all the odd multiplications IIRC, and else CIC filters are designed exactly to avoid the multiplications
<pepijndevos> lkcl_, my signals are in a map, which may make them "invisible"? Not sure how it works internally. but the traces= parameter should be fine.
<pepijndevos> uhoh... should a signal name be a valid identifier?
<pepijndevos> GTKWave is not happy with my names
<lkcl_> pepijndevos: take a look at the yosys graphviz, "show top" (or whatever module)
<lkcl_> you'll soon find if they're an AST of logic or *actual* signals
<lkcl_> i.e. if you've made a map of an *expression*, then that's not been assigned to an *actual* Signal(), has it?
<lkcl_> that being the case, why would it turn up in the gtkwave output?
<lkcl_> make sense?
<pepijndevos> Yea
<lkcl_> the "solution" is therefore to explicitly put actual Signals() into the "map", then explicitly assign to each.
<lkcl_> _then_ they'll show up in gtkwave... and incidentally massively reduce the amount of logic duplication that yosys has to deal with (remember i mentioned that yesterday-ish? :) )
<pepijndevos> That's what I have and it actually works. I was just doing weird things.
<lkcl_> :)
<lkcl_> it would be "nice" if nmigen created intermediary signals automatically... however... what names do you give them? $1? $2? $10000?
<lkcl_> oooOoo :)
<lkcl_> that's frickin funny. a spreadsheet in an FPGA / ASIC :)
<pepijndevos> coming to a nuclear power plant near you soon!!
<lkcl_> aw god!
<pepijndevos> Now I just have to implement 200 more functions
<pepijndevos> and make my parser not break on spaces
<lkcl_> pepijndevos: are you doing a "parser" parser? as in, LALR? if so, do investigate python-ply (or its successor, sly)
* lkcl_ really likes ply, despite it being "retired"
<pepijndevos> I'm using the tokenizer in openpyxl with parsy.
<pepijndevos> I should also look into making it less... eventually consistent. SUM should not output intermediate results, which may get sampled somewhere.
<lkcl_> yuk :)
<lkcl_> that example's... unreadable
<pepijndevos> It's... different
<pepijndevos> But when you already have a tokenizer and just need the AST bits, it works quite nicely.
<lkcl_> at least it's based on a well-established proven concept (lex / yacc)
<lkcl_> yeah that makes sense
<lkcl_> the problem is: whitespace handling.
<pepijndevos> why?
<lkcl_> i mean: lexx/yacc (and ply / sly) solved whitespace handling a long time ago
<lkcl_> consequently i "trust" it if you know what i mean.
<pepijndevos> *shrug* what I have works and is quite simple, I'm just not handling all tokens yet.
<pepijndevos> It just literally has a whitespace token
<lkcl_> simple is important :)
<lkcl_> after 10+ years i finally fixed the python-ply "GardenSnake" example :)
<lkcl_> it was a bit of a pig. python's whitespace rules in no way fit into standard parsers. i needed an additional "lexer pass" to insert extra (fake, silent) tokens.
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<tpw_rules> an excel accelerator card would probably make the most difference to business computation speed than any other product
<Stary> now you need to also make a VBA soft core ;)
<FL4SHK> Stary: wait, are you someone who hangs out on EFnet, or at least did, for 3DS stuff?
<FL4SHK> I swear I recognize your username at least
<Stary> both - i was around in the 3ds community and still idle on efnet :P
<FL4SHK> ah, yes
<FL4SHK> The 3DS community is probably dying down at this point
<FL4SHK> why people can't stick to making homebrew for ye olde systems, I don't know
<FL4SHK> Stary: so what brings you to nMigen?
<Stary> FL4SHK: well, mainly "getting tired of verilog's shit" :P
<Stary> i've come to appreciate the control you get on the python side though
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<Lofty> <Stary> FL4SHK: well, mainly "getting tired of verilog's shit" :P <-- I work on a toolchain and somehow manage to have mostly avoided Verilog. I aim to keep it that way.
<Stary> excellent
<FL4SHK> Stary: yes, Verilog is a piece of crap, really
<FL4SHK> it's not a good HDL
<FL4SHK> like, ignoring the simulation and synthesis mismatches that can occur in it
<DaKnig> great tools tho
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<DaKnig> how do I add assertions?
<lkcl_> DaKnig: what are you trying to do?
<DaKnig> I have something that must hold, I want to test that it does hold in all cases in a simulation
<lkcl_> if you are thinking, "hmm i really want to verify that certain things are true/false, just like i would in e.g. python or c++" then that is called "a formal correctness proof"
<DaKnig> formal proving wouldnt help much there
<lkcl_> if however you are running a simulation, then, um... just get the value and use python unit test assertions
<DaKnig> wait in pyhton you dont have formal correctness proof builtin
<lkcl_> exactly like any other python unit test
<DaKnig> what are you talking about
<DaKnig> neithter you do in C++
<DaKnig> not builtin
<lkcl_> stop
<lkcl_> read it again without the cross-over
<lkcl_> i was typing a guess at an answer _before_ you wrote that you were doing a "straight simulation not a formal proof"
<DaKnig> I want to test that on verilog level
<DaKnig> my code omits verilog and I want to test that as integrated with other verilog code
<lkcl_> ok then the answer to that starts from "if however..."
<lkcl_> ah then you are stuck
<lkcl_> because verilog cannot do python-like "asserts"
<lkcl_> because, well, duh, it's not python
<lkcl_> there is a solution however
<lkcl_> use something called cocotb
<lkcl_> this takes *verilog* (or vhdl), compiles it to c using verilator
<lkcl_> then *annotates* that in such a way that it can be single-stepped... *from python*
<lkcl_> and allows you to interact with the *verilator* simulation... *from python*
<lkcl_> at that point you *can* get the results of the unit under test, and you *can* do "python style asserts".
<DaKnig> VHDL has asserts... I assumed Verilog does too?
<DaKnig> doesnt at least SV have assertions?
<daveshah> SystemVerilog does
<lkcl_> from what i understand, verilog and vhdl asserts only apply when you run them through formal correctness proofs.
<DaKnig> no
<daveshah> They apply to simulations too
<lkcl_> they _might_ work in simulations
<DaKnig> assert statements just state what you assume
<lkcl_> then i have no idea, other than "try it out".
<DaKnig> they dont mean "do this or that in sim and this or that in synth or formal proof"
<DaKnig> useful sims would actually check them each time something changes
<lkcl_> it *might* be the case that if you add "m.d.comb += Assert(something)" in nmigen, it gets passed through to the ilang
<lkcl_> which, if converted to verilog would result in a verilog assert.
<daveshah> Yes, it does
<lkcl_> daveshah: that's cool.
<daveshah> It certainly goes to the ilang
<daveshah> I'm pretty sure the Yosys verilog backend emits a corresponding assertion too
<lkcl_> DaKnig: ok, there's the answer. import the nmigen formal "Assert"
<lkcl_> from nmigen.asserts import Assert
<daveshah> Yes, it does
<lkcl_> and just use it. m.d.comb += Assert(...) or sync +=
<DaKnig> can somebody give an example with working code that does that
<DaKnig> ?
<DaKnig> lkcl_: I'll take that last suggestion
<lkcl_> m.d.comb += Assert(5 == 3)
<lkcl_> yep, it works. one of the formal correctness proofs has "assert" put into the .ilang file
<lkcl_> daveshah: the bug turned out to be *really* obscure. to do with the implementation of PowerISA "cmp", believe it or not
<lkcl_> the clue was "0xaaaaaaaa memory comparison is not equal to 0xaaaaaaaa"
<lkcl_> self-evidently, it is :)
<DaKnig> when comparing, both sides are zero-extended to the same width first right?
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<daveshah> lkcl_: oh that sounds like fun debugging! Good work
<daveshah> I had a horrible one trying to get Linux running on or1k in the early days of trellis. Turns out a bug in Yosys had totally destroyed the TLB
<DaKnig> can I have cases in a switch statement that accept "this range"?
<DaKnig> I dont see any examples for `m.Elseif`
<DaKnig> my gut tells me that I should check every little detail in a lang I am not comfortable in, look for examples for each thing, and here I can not find any
<DaKnig> does that even exist?
<DaKnig> ah its called Elif.
<lkcl_> DaKnig: yes. m.Elif :)
<DaKnig> all the different langs doing it differently confuses me
<DaKnig> VHDL iirc uses elsif, C uses else if, python ofc uses elif
<lkcl_> DaKnig: there's variants of "cmp" (when "L=0") that effectively make the numbers being compared 32-bit, and in some cases 32-bit signed.
<lkcl_> it's quite odd
<DaKnig> cmp? L=0?
<DaKnig> did you get the wrong person?
<DaKnig> I have no idea what you are talking about
<lkcl_> "<DaKnig> when comparing, both sides are zero-extended to the same width first right?"
<lkcl_> which was right after i mentioned that i am debugging the PowerISA "cmp" implementation in libre-soc
<DaKnig> ah oops
<DaKnig> I mean comparison operators of nmigen
<lkcl_> i deduce from your confusion that you were asking about nmigen compares :)
<DaKnig> sorry
<lkcl_> lol
<DaKnig> :-)
<DaKnig> the smily looks a bit lopsided over here but thats alright
<lkcl_> honestly i'm not sure. i've never tried to do a >/=/< on anything other than exactly-equal-sized Signals
<lkcl_> it could well be the case that they're truncated rather than extended
<DaKnig> `m.If(Signal(32) == 0)` is a reasonable thing to do
<lkcl_> bottom line: i wouldn't take the risk, and would make an intermediate signal that's the right size
<lkcl_> ah yes, that's different
<DaKnig> its not?
<DaKnig> 0 is converted to const
<DaKnig> of length 1
<lkcl_> however... i remember 2 years ago trying that and learning the hard way to make sure to do
<lkcl_> m.If(Signal(32) == Const(0, 32))
<lkcl_> however in the intervening time, it could have changed.
<lkcl_> my advice: don't take the risk.
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<whitequark> ah yes, lkcl is again advising other people on topics he doesn't understand
<whitequark> every goddamn time someone asks a question in the channel. i'm so tired of this
<lkcl_> whitequark: i'm going to be really honest with you. i thought about what approach to take if you did this again
<lkcl_> i considered simply treating you exactly like you treated me, responding, "tough, deal with it"
<lkcl_> however i am not that kind of person
<lkcl_> i am however getting quite irritated at your lack of empathy and lack of tolerance
<lkcl_> i am right here. you do not need to speak of me in the third person. i am right here.
<lkcl_> being absolutely honest, you are being rude, intolerant, and your "targetting" of me may also be viewed as discrimination
<lkcl_> there is absolutely no need for it
<lkcl_> so please.
<lkcl_> if you're "triggered" by something that i say, take a deep breath.
<lkcl_> i deeply appreciate that you're able to be honest and tell me - everyone here - that you're irritated by my lack of knowledge
<lkcl_> or limitations
<whitequark> lkcl_: i do not appreciate the way you are giving others advice here without first making sure you understand what you're talking about
<whitequark> i made this clear multiple times in the past
<whitequark> you decided to disregard this
<lkcl_> however we all have to get along. the project that i'm doing is *going* to get done
<lkcl_> whitequark: no i did not. i don't know the answer, and i said so.
<lkcl_> so i described to DaKnig an "approach".
<lkcl_> i SPECIFICALLY SAID, "i do not know the answer"
<lkcl_> and gave him some recommendations - in the absence of anyone else providing advice - which i have found to work
<lkcl_> now that you are here, you can advise him - and me - of the *correct* way, from your full and detailed understanding of nmigen
<DaKnig> I thnk I'll use 0 and assume nmigen is doing something sensible like zero-extending :)
<DaKnig> because writing C() every damn time is annoying
<lkcl_> however continuously nit-picking and "trying to make me look bad" - repeatedly - is called "discrimination".
<DaKnig> I hate Verilog integer constants and it reminds me of them
<lkcl_> DaKnig: now that whitequark is here, she can advise you correctly.
<DaKnig> yes I'd like to hear that
<lkcl_> i'd like to know as well, because there's several places where i've put Const(...) into libresoc code
<DaKnig> lkcl_: why Const and not C?
<DaKnig> being explicit?
<lkcl_> ah yeah they're the same thing, different names for the same class
<whitequark> DaKnig: the rule of thumb is that all nmigen arithmetic (and comparison) operations work on the mathematical value
<whitequark> as long as you don't assign any part of the expression to an intermediate signal, operands and subexpressions are zero/sign-extended as needed
<lkcl_> whitequark: thank you for explaining that.
<whitequark> let's take a look at the specific case of `with m.If(sig == 0):`
<whitequark> first, 0 is value-cast to Const(0, 1):
<whitequark> >>> Value.cast(0)
<whitequark> (const 1'd0)
<whitequark> second, if `sig` is longer than 1 bit, Const(0, 1) is zero-extended (since it's unsigned) to the appropriate width, giving Const(0, len(sig))
<DaKnig> yea I assumed that much
<whitequark> lkcl_: you're right, i overreacted, and i treated you unfairly in this situation. i'm sorry; i'll do better next time.
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<lkcl_> whitequark: i'm really touched that you said that. thank you
<lkcl_> excuse me
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<Yehowshua> Is there an idiomatic way to sign exten a value? Or is Cat the way to go?
<whitequark> Yehowshua: not yet;
<whitequark> turns out it's surprisingly hard to design one
<Yehowshua> I bet
<DaKnig> what's hard about it?
<whitequark> DaKnig: take a look at the linked issue (and the issue it links to)
<whitequark> multiple choices with subtle tradeoffs where there isn't clearly a better one
<DaKnig> if you know the required width of the result, its just taking [-1] and extending it, no?
<DaKnig> ok
<whitequark> actually implementing sign extension for a single specific case isn't hard at all
<Lofty> Plus me being a bit of a pain when it comes to "easy options" in the discussion.
<Yehowshua> I'm guessing whitequark is back from vacay
<Lofty> I feel like the way I write nMigen is perhaps a bit non-standard
<DaKnig> this issue talks about shape conversion in general though
<DaKnig> shrinking is harder than extending
<whitequark> Yehowshua: i'm not
<Lofty> That's...tomorrow, right?
<whitequark> yeah
<DaKnig> yikes. working from vacation. sry for bothering you wq
<Lofty> Heh. This is supposed to be my summer holiday from university. Hasn't felt like it in the least.
<Yehowshua> Or maybe hanging out on #nmigen is just so relaxing
<whitequark> not particularly, i'm just not used to vacations
<Yehowshua> Nobody will blame you if you log off... Get some you time in
<Lofty> ...I don't think I'd even know how at this point (I know you're not talking about me, but)
<whitequark> yeah kinda in the same boat
<Lofty> I've been coding for so long's kinda all I know how to do
<Yehowshua> Lofty, you're in University non?
<Lofty> As I mentioned earlier, yeah
<Yehowshua> Grad school?
<Lofty> I'm an undergrad
<Yehowshua> 👌
<Lofty> "Hey, Lofty, you should go out and enjoy the opportunities University brings!" - basically everybody I've talked to
<Lofty> But I've yet to find any
<Lofty> For some reason the idea of going into painfully-loud clubs with a bunch of chronic alcoholic flatmates doesn't appeal to me
<Yehowshua> Hmm
<whitequark> ... i was about to ask
<Yehowshua> I went to tour an old lighthouse last week
<Yehowshua> And I also make short films on the side
<Yehowshua> Does your uni have any attractions?
<Lofty> The biggest attraction it has is being about three hours away (including bus and train) from home
<Lofty> Other than that, it's out in the sticks where post-industrialism murdered the local economy
<Lofty> At least it has a forest to it
<Yehowshua> Where on earth are you - if I may ask
<Yehowshua> Sounds brutal
<Lofty> Middle of England
<sorear> three hours away (including bus and train) — oh good, there's a bus and/or train tere
<Lofty> It prospered as industrial powerhouses in the early to mid 20th century, and then as industry moved elsewhere, so did the money
<Yehowshua> sorear LOL
<Lofty> The North of England has had a bunch of investment and infrastructure
<Lofty> But the Midlands have not
<Lofty> And, well, when was the last time you saw pottery in demand?
<mwk> ... what is a vacation anyway
<Lofty> mwk: apparently it involves taking a break from coding. I don't quite get it either.
<Yehowshua> A vacation is when you go to the beach and buy excessive amounts of ice cream
<mwk> like I'm used to vacations with my family that just resulted in me working more to dissociate from having them in close quarters
<whitequark> mwk: it's what you take when you feel that burnout will soon prevent you from fulfilling your existing obligations
<Yehowshua> My family made me go with them on vacay once and told me there was only one rul
<Yehowshua> no coding
<Yehowshua> **rule
<whitequark> yeah, my parents tried to do that a few times
<whitequark> i moved out to live on my own as soon as i had the means and haven't talked to them since
<whitequark> A+ would recommend to everyone
<Yehowshua> Mine gave up the first time they tried
<whitequark> "no coding" can be nice and healthy when it's your own decision, not the decision of your abusive family which loves dictating what you can and cannot do on any other time of year as well
<Yehowshua> Well, my family dynamic is usually pretty healthy. I guess I'm one of the more fortunate
<Lofty> It's difficult to tell whether my dad is a bad person or not, but... He's definitely an intense person, and he generally considers himself to be right no matter what.
<Yehowshua> What I really want to know is who is hell__?
<Lofty> A friend of mine, at least
<whitequark> Lofty: someone doesn't need to be a bad person to be abusive
<whitequark> knowing that simplifies the decision, usually
<whitequark> "generally considers himself to be right no matter what" = "run and never look back"
* hell__ pops up
<DaKnig> mwk: vacation is when you force yourself to do something you dont usually do for an extended amount of time
<DaKnig> :)
<Lofty> I get misgendered on a daily basis ^.^
<whitequark> let's extend that with "also never talk to him again"
<whitequark> see, very easy
<Lofty> Hurray for being NB >.>
<mwk> ... is it bad if I *wanted* to get kicked out when coming out as trans to my family because that'd actually simplify matters
<Yehowshua> Did hell__ just enter the conversation?
<hell__> Yehowshua: you just highlighted me twice
<Yehowshua> Yup haha
<Yehowshua> Just wondering about your name
<Lofty> Well, I presume maintaining Coreboot is hell__
<Lofty> :3
<Yehowshua> Have you heard about reboot?
<Yehowshua> **oreboot
<DaKnig> I dont like sticking in one place in the industry for too long; I dont really take vacations
<hell__> Lofty: that's why I'm taking a vacation now
<DaKnig> embedded programming -> hardware-> algorithms -> weird types of alternative logic systems -> ...
<Lofty> Ah, I see.
<Yehowshua> mwk - I've noticed that most of my FPGA friends never quite fit in
<Yehowshua> Not necessarily being trans, but lots of other things too
<hell__> I picked this nick because it describes myself rather well
<Lofty> Well, uh, there are Certain People in the FPGA sphere who I'd rather not fit in with at all, but anyway
<Yehowshua> shots fired huh?
<DaKnig> much drama today :)
<Yehowshua> I feel like I may have missed something haha
<Lofty> Nah, this drama goes back quite a lot further, and it's also very much off topic, so
<Yehowshua> na problema
* Lofty idly wonders what the IRC equivalent of subtweeting is
<whitequark> ... huh, first known use of "subtweet" is from 2009
<whitequark> i thought it's more recent, but of course it's not
<smkz> おれboot
<smkz> hi whitequark
<DaKnig> I wish I could finish my VGA to HDMI converter at soe point
<DaKnig> feels like I spent eternity on this crap
<awygle> hooray my lights work
<whitequark> hi smkz!
<Yehowshua> Looking at current plane ticket prices - now is a great time for a vacay actually!
<Yehowshua> Ignoring other certain global phenomena
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<awygle> whitequark: sweet job w/prjbureau!
<Lofty> ^
<smkz> ^
<whitequark> thanks
<whitequark> what's left is mostly device config bits, which are honestly pretty easy
<whitequark> plus some toplevel docs
<whitequark> maybe in a few weeks
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* tannewt looks up prjbureau
<tannewt> neat! love seeing more at the low end
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