#nmigen on 2020-09-16 — irc logs at freenode.irclog.whitequark.org

2020-09-07 15:44 ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting September 14th

01:09 <awygle> hm. cxxsim/cxxrtl can only handle synthesizable verilog. verilator can handle this simulation model but not nmigen code. i guess i need to either output the nmigen as verilog and include the output in a verilator sim or try to simultaneously run cxxrtl _and_ verilator C++, which seems.... like a bad idea lol

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18:00 <mithro> whitequark: Finally finished of the sphinxcontrib-hdl-diagram stuff -- https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/directives/hdl-diagram.html#nmigen

18:02 <mithro> whitequark: Still a few more things to clean up around using yowasp and similar stuff

19:25 <whitequark> mithro: thanks! that'll come in very handy with nmigen docs

19:29 <d1b2> <Banana Phone> I finally got my ripple carry adder working

19:29 <d1b2> <Banana Phone> Once I learn nmigen I'd be happy to contribute to the documentation if that'd be helpful

20:18 <mithro> @whitequark Please do report bugs, the antmicro team will work on fixing them but it might take a bit

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20:36 <tannewt> looks neat mithro!

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22:23 <_whitenotifier-f> [nmigen] jfng synchronize pull request #499: hdl.mem: document ReadPort and WritePort. - https://git.io/JU4Ve

22:23 <_whitenotifier-f> [nmigen] jfng commented on pull request #499: hdl.mem: document ReadPort and WritePort. - https://git.io/JURmv

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