<yuriks>
DaKnig: what's the usage pattern for that queue? Is it a constant feed from each input, is it bursty or unpredictable? etc.
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<yuriks>
you can make a FIFO with two inputs, but something else might be a better use of resources for you
<DaKnig>
it's bursty for each input; I think the bursts might be aligned or not depending on choices I did not make yet.
<yuriks>
(needs a memory with two write ports, or double-pump the fifo)
<yuriks>
you could have 2 separate FIFOs and then just load-balance reading between them
<DaKnig>
I have more than 2 sources :)
<yuriks>
ah
<yuriks>
sorry, I'm not sure why I was assuming that
<DaKnig>
operating x FIFOs does not sound too elegant
<yuriks>
for an arbitrary number of inputs I think most of the reasonable solutions are going to have tradeoffs
<yuriks>
if you're fine with (bounded) blocking you could also round-robin between which input you feed from each cycle
<yuriks>
you're not going to be able to continuously feed stuff in anyway unless the consumer of the queue operates at a much faster speed
<yuriks>
if the bursts are aligned a lot of the time you could have a FIFO of width n_inputs * data_size, then you load all the ready inputs into it at the same time
<yuriks>
(this also in theory lets you easily pop N items at once from the output)
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<_whitenotifier-3>
[YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JUmLm
<DaKnig>
I can guarantee that if I have some number n of producers, there's always enough clocks for the consumer to read the things out
<DaKnig>
so that s not a concern
<yuriks>
can you just read round-robin then?
<DaKnig>
yuriks: gotcha. just read the logs.
<DaKnig>
the problem with round robin is that it stops the producers I think?
<DaKnig>
ah no. just the writing part.
<yuriks>
yes, they'll block for up to N cycles
<yuriks>
but then, assuming they're a pipeline anyway, that's going to align their outputs to the queue duty cycle
<yuriks>
so I think it should be fine? since you said the producers shouldn't overwhelm the conusmer
<yuriks>
having multiple FIFOs never blocks the producers, but then you're trading that for max queue depth
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<whitequark>
DaKnig: < DaKnig> in VHDL/Verilog you can describe any digital haradware . in nmigen you cant.
<whitequark>
this is not actually true
<whitequark>
first, all of these languages let you connect primitives with wires, which trivially let you describe anything your backend can process
<whitequark>
but if we eliminate that from consideration, there are plenty of things that cannot be described in synthesizable Verilog
<whitequark>
for example, an FF with both async set and async reset
<whitequark>
< moony> what'd be the best way to create an all-ones value for any length signal?
<whitequark>
moony: DaKnig: the way I usually write it is ~0
<whitequark>
although C(-1) also works, ~0 makes the intent more clear imo
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<whitequark>
<TiltMeSenpai> is there a way to have a sim-only string "signal" to help with debugging a CPU design
<whitequark>
have you looked at signal decoders?
<whitequark>
regarding unused signals being optimized out: you can *definitely* rely on unused comb signals being optimized out. although not currently described anywhere as a part of the language contract, it should be, so that you (and awygle and everyone else not quite comfortable with the idea) would be able to rely on it
<whitequark>
sync signals are more complex though!
<whitequark>
for now, I wouldn't tell you to rely on those being optimized out, because synthesizers are generally more cautious about removing registers
<whitequark>
they'll generally be, but I'd have to look carefully at every supported backend before I can even consider making it a part of the language contract
<whitequark>
oh, sorry, you've already had decoders recommended
<Yehowshua>
Also, I clang that comes with MacOS is messed up in general, which cxxsim python finds. Its possible to override this behavior in `cxx.py`, but I remember that there was some discussion about allowing overrides.
<Yehowshua>
Should I make an issue for that?
<Yehowshua>
I just use homebrew's clang which works like one might expect
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<whitequark>
Yehowshua: how does the built-in clang fail in this case?
<whitequark>
this is orthogonal to overrides; overrides are important but so is out-of-the-box experience
<whitequark>
this is going beyond the usual macOS clang weirdness
<Yehowshua>
It's also clang11.03?
<whitequark>
no no
<whitequark>
it's *appleclang* 11.03
<whitequark>
the apple clang versioning has nothing to do with upstream clang versioning whatsoever
<Yehowshua>
Thank you - yes appleclang
<whitequark>
it's forked off some random revision from trunk
<whitequark>
no they won't tell you which
<whitequark>
though i think if you have friends who are apple employeers they might tell you
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<Yehowshua>
haha - yeah, the first thing I do when I get a Mac is brew install coreutils and friends
<Yehowshua>
MacOS defaults are weird
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<sorear>
by way of example, the most recent upstream tag is 11.0.0-rc2
<sorear>
there is no 11.03
<whitequark>
the reason you don't have recent coreutils or other GNU software is because of GPL3
<whitequark>
but clang is not GPL3
<Yehowshua>
Yeah
<whitequark>
sorear: back in llvm 4.x days appleclang had version 6
<whitequark>
not even the major version has any relation
<whitequark>
it's just a completely arbitrary number apple came up with
<whitequark>
because fuck you, that's why
<Yehowshua>
Apple open source is weird
<Yehowshua>
They have their FOSS webkit and internal webkit
<Yehowshua>
same with swift and others
<whitequark>
it's not unreasonable that they have a private fork of llvm/clang
<whitequark>
e.g. rust also has a private fork of llvm
<Yehowshua>
And IIRC, they hired lattner for the bulk of clang way back when
<whitequark>
it *is* unreasonable that they don't tell you even approximately what upstream version of clang it is
<Yehowshua>
Yup! My policy is don't even bother supporting their defaults
<whitequark>
the problem is that your python is built with the apple clang
<whitequark>
why's that?
<whitequark>
hm, wait, it's in "Cellar" which means it's a homebrew thing
<Yehowshua>
I can rebuild it, homebrew upstream bottles are built with apple defaults so that homebrew installs easily onto Macs
<whitequark>
right, so if you rebuild it, you should have cxxsim working out of the box
<Yehowshua>
Well yeah, I'd have to rebuild python with homebrew's clang
<whitequark>
it's really not clear what is a good way to discover a working system compiler in general
<whitequark>
like... i could depend on cmake. i do not want to depend on cmake
<Yehowshua>
No no no
<whitequark>
there's basically no answer to this which isn't profoundly cursed
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<Yehowshua>
I think requesting MacOS users install homebrew's clang is reasonable - most of us have to do something like that anyways at some point in time
<whitequark>
the problem is configuring the compiler
<whitequark>
(and the linker)
<Yehowshua>
Well, it works out of the box if you install homebrew's clang and put it on the path
<whitequark>
that is an accident
<whitequark>
it *happens* to work out of the box
<whitequark>
but nothing in the code actually ensures it does, you're just lucky
<whitequark>
python could have well been built with incompatible flags, then it won't work
<Yehowshua>
Ah, I use homebrew's python3
<Yehowshua>
which are built with the same flags
<Yehowshua>
Apple's python3 is garbagio
<Yehowshua>
Most MacOS users know to avoid it
<whitequark>
let me elaborate
<whitequark>
currently, sim.cxxsim uses the flags your python binary was built with
<whitequark>
if it was built against apple clang, there's no guarantee those flags will be compatible with any other clang binary
<Yehowshua>
yes, I understood as much
<whitequark>
clang doesn't break things often, so this happens to work
<whitequark>
but it's just an accident
<whitequark>
i'm thinking that i could try the following: if neither CXX nor CXXFLAGS is set, then use the paths from distutils. if *any* environment variable overrides are set, then don't use anything from distutils
<Yehowshua>
Sounds reasonable, combined with letting the user know CXXSim is now looking at the environment variables
<whitequark>
we don't currently do any logging from inside of nmigen
<whitequark>
that might change but i'm hesitant to do it for cxxsim alone
<whitequark>
it seems fine to make it opt-in though
<Yehowshua>
YosysWarning: Design contains feedback wire - is that a combinational loop? - thats from CXXSim
<Yehowshua>
PySim doesn't pick up on that
<whitequark>
not necessarily a combinatorial loop (otherwise I'd say so)
<whitequark>
can you give me the .il file?
<Yehowshua>
yeah - email
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<whitequark>
let me take a look
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<Yehowshua>
It occurs to me that I had mentioned I was part of LibreSociety some time ago on this channel. That is no longer the case as I was (rather forcefully) kicked out
<Yehowshua>
of LibreSOC
<whitequark>
sounds like a huge loss for them
<Yehowshua>
Only time will tell
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<Degi>
I have two modules which instantiate another module. Said module has in its constructor a "reset = Signal()" as a parameter. When I instantiate the module and leave out that parameter, nMigen gives me a driver conflict (so that I need to explicitly add a "Signal()" when instantiating the module, which fixes that issue), how can that be?
<Degi>
(It says that it is driven from multiple fragments and that the hierarchy will be flattened)
<whitequark>
Yehowshua: looking closer at your file, I'm starting to suspect this is a genuine issue in the netlist
<whitequark>
Degi: never have anything mutable as an argument default in Python
<whitequark>
this is an unfortunate and well-known footgun
<Degi>
Ah, so I should instead use something like "0" and "1" as defaults or not specify a default at all instead? Good to know, thanks!
<whitequark>
yes. tuples () are fine too, lists [] are not though
<daveshah>
> The following standards are provided to the community at no cost courtesy of Accellera via the IEEE Get program:
<Yehowshua>
Oh? As in the creators of PCI or PCIe for example, purchasing a standard doesn't enrich them
<Yehowshua>
I'm reffering to engineers
<whitequark>
daveshah: oh, interesting
<whitequark>
yeah, this seems to be the case. of course, IEEE won't skip a chance to make it more confusing
<whitequark>
Yehowshua: what I'm saying is that no one should pay IEEE for standards, because their behavior should not be rewarded in any way
<whitequark>
and, besides, that by not paying IEEE you do not harm anything or anyone except IEEE itself
<whitequark>
whose business model shouldn't exist in first place
<Yehowshua>
Ah, I missed that. What is IEEE's behavior?
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<whitequark>
charging people hundreds of dollars for a pdf (on top of charging their members) while contributing effectively nothing towards the existence of that document
<whitequark>
like I said, IEEE is a predatory publisher
<whitequark>
not quite as good of a racket as the scientific publishers, but a pretty good one, too
<whitequark>
the only example I can think of that is worse than technical/scientific publishing is the situation in some countries (Australia is one of them, I believe) where you have for-profit publishers of laws and regulations
<daveshah>
^
<daveshah>
the UK wiring regulations are like this
<daveshah>
not technically a law, but it is much harder to demonstrate compliance with the law if you don't follow them
<Yehowshua>
whitequark, you sound a lot like my friend who refuses to buy movies or do anything to enrich Comcast ha
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<Yehowshua>
But anyways, I had never heard of a complaint against IEEE before or felt this way about it. I will have to think a bit on that
<whitequark>
Yehowshua: see, movies and music are not so black-and-white, because at least *some* (pathetically low, but nonzero) amount goes to the people who actually create it
<whitequark>
but with publishers you don't even have that
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<Ultrasauce>
the noble pursuit of revenue extraction
<Yehowshua>
One of the most lucrative business models is creating and then owning a market
<whitequark>
why would you use your own money to enrich some administrator whose only purpose is rent-seeking?
<whitequark>
do literally anything else with it. give it to a homeless person. spend it on cocaine. literally anything is better than giving it to IEEE
<Yehowshua>
Vote with your wallet
<Yehowshua>
What you need whitequark is a platform
<whitequark>
ehhh
<Yehowshua>
Platform, a place to make your thoughts known
<trabucayre>
whitequark: ligen is a solution no ?
<trabucayre>
libgen
<FL4SHK>
nligen
<FL4SHK>
oh
<whitequark>
trabucayre: scihub has some ieeexplore standards but not all of them
<whitequark>
also it is not so much a "solution" as "workaround"
<Yehowshua>
whitequark, how do you feel about PCIe?
<Yehowshua>
I think its too complex
<whitequark>
the entire world cannot rely on a single Kazakhstani woman forever
<FL4SHK>
I've heard good things about PCIe
<FL4SHK>
or maybe it was ethernet
<Yehowshua>
i luvvv ethernet
<trabucayre>
whitequark: yep
<Yehowshua>
easy
<whitequark>
Yehowshua: I like it a lot, I think it's one of the most well-designed interfaces we have in computers
<whitequark>
and the fact that other interfaces have been consistently throwing out their physical layers to replace them with PCIe (or something PCIe-like) is telling
<whitequark>
it is somewhat complex, yes, but nearly all of that complexity is essential
<whitequark>
Ethernet isn't bad either, it just solves different problems in different ways
<Yehowshua>
true
<whitequark>
(Ethernet is also a good contender for one of the most well-designed interfaces in computing!)
<Yehowshua>
HDMI is also stupid simple
<FL4SHK>
VGA is easier :P
<FL4SHK>
VGA is soooooooo easy
<FL4SHK>
I did build a VGA signal generator thing in nMigen
<FL4SHK>
I should contribute it
<whitequark>
I actually would not call VGA all that easy
<whitequark>
well
<Yehowshua>
VGA max res was slightly about 1080p
<whitequark>
it's easy to get started with, that is absolutely true
<whitequark>
but it doesn't scale
<whitequark>
and if you want consistent results you're in for a challenge
<FL4SHK>
I'll have to try generating a 1080p signal
<Yehowshua>
I tried looking at DP
<whitequark>
ask any old timers about modelines
<whitequark>
that wasn't so easy was it
<mithro>
I remember modelines and being worried about destroying my CRT screen...
<daveshah>
I was young enough at that time that I was worried I would damage my laptop's LCD based on all the warnings...
<whitequark>
I'm doing this to narrow the issue down a bit
<whitequark>
ideally nmigen itself would do it, it's mentioned as a defect in the current docs
<whitequark>
but for now that should do
<Yehowshua>
OK thx. Will try that this afternoon
<whitequark>
gives me this: Module `top' contains feedback arcs through wires: serialmem.load_afifo.mem_to_load_afifo.unbuffered.rst_dec.o serialmem.load_afifo.load_to_mem_afifo.unbuffered.rst_dec.o
<Yehowshua>
Oh right timezones
<Yehowshua>
in a couple hours
<Yehowshua>
I have an idea what that might be
<Yehowshua>
lol - nMigen's soon to be stream library would solve exactly that
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<mithro>
I thought you all might be interested to know that Antmicro is actively working on a new "sphinx-verilog-domain" (https://github.com/SymbiFlow/sphinx-verilog-domain) which brings native support for documenting Verilog code into Sphinx.
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<whitequark>
hey, I for one hope I will never have to document Verilog code :p
<FL4SHK>
uh so
<FL4SHK>
would you guys like an IEEE 754 FPU?
<FL4SHK>
I could contribute it
<FL4SHK>
in nMigen, of course
<whitequark>
an FPU should not be a part of nMigen itself, just like a CPU shouldn't; but of course it is a great community project
<FL4SHK>
so an SDRAM controller is something that should be a part of nMigen?
<whitequark>
yeah. nmigen-stdio specifically
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<whitequark>
in my view, nMigen should, aside from a language, provide building blocks necessary for interoperability
<whitequark>
both between modules written by various developers, and with industry-standard interfaces
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<Yehowshua>
FL4SHK, an nMigen FPU already exists
<Yehowshua>
It took about 4 months to write
<Yehowshua>
And generates between 30 - 75 gates in Yosys
<Yehowshua>
75k
<FL4SHK>
I was going to say
<FL4SHK>
that's too small
<FL4SHK>
is it pipelined?
<Yehowshua>
Yes - you can specify how many stages
<Yehowshua>
Its mostly IEEE 754 compliant - some edge cases need to checked I think
<Yehowshua>
I don't think it was ever synthesized for a platform
<FL4SHK>
I think I still want to do my own implementation
<Yehowshua>
For sure
<Yehowshua>
It will take about 4 months
<sorear>
normally if you’re designing a fully pipelined fpu, you do combinatorial logic and rely on retiming
<Yehowshua>
I think Paul Mackeras from IBM OpenPOWER Microwatt did one in VHDL - it also took him four months
<whitequark>
can't really do that with the FOSS tools right now
<whitequark>
the FPGA tools at least
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<FL4SHK>
from the sound of it I may be able to delay building the FPU for my FPGA computer project
<FL4SHK>
seems I only need integer ops for now
<FL4SHK>
going to be porting NetBSD to the machine
<moony>
NetBSD runs on literally everything doesn't it? :P
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<moony>
Still supports VAX even
<FL4SHK>
that's one reason I was interested in porting it
<Yehowshua>
FL4SHK, ever tried RedoxOS?
<FL4SHK>
No. What's it like?
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<whitequark>
can't you rebuild anything that uses FPU with softfloat?
<Yehowshua>
It like a unix kernel, written entirely in Rust
<FL4SHK>
whitequark: yeah, I was thinking of having the machine hold off on floats for now
<FL4SHK>
it's a weird CPU that I've started designing
<whitequark>
i mean not having FPU is not unusual
<moony>
^ FPUs take up a bunch of space, so not having one is p normal
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<Yehowshua>
Yeah, you won't be able to fit more than one FPU in the ECP5 85k
<FL4SHK>
It does depend on a number of factors
<moony>
and afterward you'd be tight on space for the rest of your stuff
<FL4SHK>
I'm curious how many would fit in my Arty A7
<moony>
FL4SHK: size? Probably still only 1, maybe 2 if lucky
<FL4SHK>
I don't know the exact size, but to me, it's a pretty monstrous FPGA
<moony>
did you buy the $130 one
<FL4SHK>
no, was like, $250
<Yehowshua>
whitequark, yosys has a `-retime` option non?
<moony>
or the $250 one
<FL4SHK>
I did this on purpose because I was intending on building a daily driver machine with it
<moony>
FL4SHK: Ok you have the largest A7 then, 100 logic cells
<whitequark>
Yehowshua: yosys has many options but not all of them do something useful
<moony>
100k*
<FL4SHK>
I thought it was more like 120k?
<FL4SHK>
If I can fit one FPU I'm probably good...
<Yehowshua>
Once you start needing multiple FPUs, you're basically looking at Xilinx Ultrascale...
<moony>
also, daily driver?
<moony>
what do you mean by that?
<Yehowshua>
My previous lab had a few
<FL4SHK>
machine I want to use as my main computer
<sorear>
if you designed a multicycle fpu you could fit it easily
<FL4SHK>
like a single board computer or something
<moony>
...why use an FPGA as your main PC? :P
<FL4SHK>
because I want to be the one who designed my main PC
<moony>
also, as sorear did say, just design one that isn't silly pipelined and it'll fit
<FL4SHK>
I'll just have to see
<moony>
iirc some of the smallest designs (i.e. 8087) were ucoded
<FL4SHK>
also, 256 MB of RAM really doesn't cut it
<FL4SHK>
I'll want to get a fancier dev board
<sorear>
also there are like six good (maintained by various academic groups) pipelined fpus in the open sector
<FL4SHK>
one with SODIMM slots
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<FL4SHK>
sorear: I might cop out and grab one of those
<FL4SHK>
I don't really *want* to
<whitequark>
softfloat might or might not be usable as a daily driver
<sorear>
I’m not sure if any of them are (n)migen (apart from what Yehowshua posted, idk its quality)
<whitequark>
i mean, i can't imagine using a softCPU daily at all, even my laptop, which is hundreds of time faster than anything you can put in a commercial FPGA, feels too slow most of the time
<moony>
^ FPGAs are limited by clockspeed a good bit, too
<moony>
a large design has to run at a lower clock, you can't clock it at the FPGA's max or it literally just won't work (gate latency)
<whitequark>
FPGAs don't really have a maximum clock speed do they?
<moony>
whitequark: not really , but there's a max in the spec you probably don't want to exceed
<daveshah>
There is usually a maximum frequency for the global clock tree
<whitequark>
right, that
<whitequark>
but you're not going to reach that even with very simple logic, would you?
<whitequark>
it probably matters only if you're using the FPGA as an overpriced PLL
<whitequark>
or something like that
<daveshah>
Yeah, usually it ends up around the 1 or 2 logic level mark
<daveshah>
It might affect interfaces where you do one layer of gearing in the fabric
<whitequark>
oh, right
<daveshah>
Hard IO gearing usually has its own faster clocking options
<daveshah>
Either way, not exactly going to be close to the maximum useful frequency for a soft CPU
<whitequark>
there's the trick where you use a barrel processor and pipeline the hell out of it
<whitequark>
so there's only one logic level between every register
<whitequark>
that could maybe approach it
<whitequark>
but probably not really, since routing delay is also a thing
<Sarayan>
routing and block traversal
<Sarayan>
traversing a cyclone v lab is around a nanosecond, roughly
<Sarayan>
so you're not going to do a GHz scale processor in a cv fpga
<Sarayan>
also, intel makes no sense, news at 11
<whitequark>
cyclone v is altera though
<Sarayan>
then altera makes no sense, news at 11
<Sarayan>
they have in they data files a "parallel frame size", of which depends the size of all frames and in particular the config ones
<Sarayan>
32 "strips", hence the name parallel
<Sarayan>
the number of config bits per strip one can put in such a frame is, at is obvious, that value... plus seven
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<daveshah>
tbf, I don't think I've seen a single FPGA which has an entirely logical bitstream structure
<Sarayan>
tbh, it's not so bad in altera's case
<cr1901_modern>
daveshah: At least you found an FPGA family where they consistently start counting from "0" :)
<whitequark>
daveshah: add CPLDs to that list imo
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<mithro>
whitequark: [this is a terrible idea, but I just had to say it] I wonder if nmigen should take the sphinx compatible documentation inside the Python code and use it to generate sphinx compatible documentation for the output verilog :-P
<whitequark>
not unless you add support for roundtripping comments through RTLIL to Yosys
<mithro>
whitequark: How does the nmigen verilog output look? Is it better than the output from migen? I forgot what your thinking was around that?
<whitequark>
it's somewhat worse
<whitequark>
it would have been around the same but Verilog is a hellish language and I wasn't able to extend the write_verilog pass to improve the output, so fa
<mithro>
"wasn't able to extend" == "did not have the time" or "it would be technically hard"?
<whitequark>
it has defeated several people who attempted to do it
<whitequark>
me, Lofty, and IIRC someone else
<whitequark>
I know how to do it, but the effort required is immense
<whitequark>
and so far I spent time working on more pressing things instead
<Lofty>
It's very much the latter
<Lofty>
Verilog as a standard is full of landmines
<Lofty>
The biggest one we've had is for example the Verilog ?: operator
<whitequark>
I mean, it's not just the standard, in this case the frontends actually implement what the standard says
<whitequark>
but yeah
<mithro>
I hate the word latter -- it always confuses me
<awygle>
ever since i learned (in here) how to remove the attribute comments from the nmigen verilog output it's much more readable imo
<whitequark>
mithro: honestly, the answer to your question is "it is technically hard and it would therefore take a lot of time"
<whitequark>
you basically have one option and it is to construct a Verilog frontend in reverse
<whitequark>
you can skip some steps and it makes other steps exponentially harder
<whitequark>
e.g. write_verilog skips AST construction and that makes inlining expressions almost impossible
<Sarayan>
little RE game. From the two values on the left find a way to compute the value on the right
<Sarayan>
// 7024 48 -> 7328
<Sarayan>
// 5304 40 -> 5600
<Sarayan>
// 9948 4 -> 10208
<Sarayan>
// 3928 8 -> 4192
<Sarayan>
// 3412 12 -> 3680
<Sarayan>
note that there could be a rouding up to 32 somewhere in the formula
<Sarayan>
meh, v1+v2+256, too easy
<Sarayan>
damn, I was hoping for a challenge :-)
<Sarayan>
(height of a firmware column, padding indicated in the data files, actual length of a cram frame)
<Lofty>
Oops :P
<Lofty>
Also, lest people complain, there's always #prjmistral
<Sarayan>
sure
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<mithro>
Probably not much help, but I wonder if something like verible could potentially be used help as it's designed more around reformatting / restructuring verilog file
<Sarayan>
the google thing?
<whitequark>
mithro: I'm very much not interested in dealing with Verilog semantics directly
<whitequark>
either through Verible or otherwise
<mithro>
whitequark: I totally understand that!
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<FL4SHK>
I think it's feasible for a pipelined implementation of a multi cycle design to not take up that many more LUTs?
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<DaKnig>
doesnt pipelining basically take just as many LUTs but more dffs?
<mwk>
it can also increase LUT usage if the dffs happen to be inserted in the middle of logic that would otherwise be packed into a single LUT
<mwk>
(that + of course you may need extra logic for the control signals involved)
<DaKnig>
@Yehowshua about hamster works- from what I gather, people didnt stop asking him to help with their HDL homeworks or whatever, so he couldnt keep this website up... he lurks in one Discord server I was on. the wiki is on wayback machine and is a great resource.
<DaKnig>
Yehowshua: about HDMI being easy- do you mean maybe DVI?
<DaKnig>
most things I find online are actually DVI even though they claim to be HDMI
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<awygle>
mithro: is that the intended use case of verible, linting/formatting?
<mithro>
whitequark: Using my resources to pick up the "boring but needed" type projects is some of what I'm trying to do...
<mithro>
awygle: Yes
<awygle>
can't decide if that's disappointing or encouraging frankly
<DaKnig>
whitequark : my FPGA is rated for 1.4GHz ; you can get to 1.5GHz output rate over HDMI with some trickery. but its not rated for that. just saying, it's possible... (ofc if you try to run any actual logic at that rate, even with one LUT my FPGA would have trouble getting over 400MHz)
<awygle>
mithro: are these google-affiliated?
<mithro>
awygle: We have been funding Alain and Antmicro to do work on them
<mithro>
And have some prototypes of interfacing them to Yosys / Verilator
<awygle>
i see
<mithro>
Kinda similar to how Yosys interfaces to Verific but at a slightly different layer
<awygle>
are y'all funding anything else interesting in this space?
<DaKnig>
Lofty: what's the problem with ?:
<DaKnig>
is it much different from how C does it?
<Lofty>
No, it has nonintuitive extension properties
<Lofty>
If you have `input [3:0] A; input S; output [7:0] Y;`
<Lofty>
`always @* if (S) Y = $signed(A); else Y = A;` does what you think it does
<Lofty>
If S is true, it gets sign extended, else it gets zero extended
<Lofty>
If you rewrite this with a ternary operator
<Lofty>
`always @* Y = S ? $signed(A) : A;`
<Lofty>
The $signed() has no effect here
<Lofty>
So it becomes `always @* Y = S ? A : A;`
<Lofty>
Or `always @* Y = A;`
<Lofty>
DaKnig: ^
<DaKnig>
in Verilog things are by default signed right?
<DaKnig>
I didnt program a lot in Verilog...
<Lofty>
No, they're by default unsigned
<Lofty>
Like nMigen
<DaKnig>
ok
<DaKnig>
well this kinda makes sense; is that because both branches of the ?: have to be the same type?
<Lofty>
Well, specifically the Verilog standard requires ?: to always zero extend
<Lofty>
So the behaviour changes if the arguments to ?: are not of the same width
<Lofty>
whitequark tripped over this while working on the write_verilog_inline PR
<DaKnig>
C has similar crap :)
<Lofty>
As I'm aware, but this issue is Verilog specific
<DaKnig>
(I only mentioned this since that's what Im more familiar with; had to work with the C standard... inconsistancies everywhere :))