ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting September 14th
* cr1901_modern thinks of a contest to create the _slowest_ RV32I CPU that fits into a certain-size FPGA
<cr1901_modern> that passes rv32-formal*
<_whitenotifier-f> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JU4aK
<_whitenotifier-f> [YoWASP/nextpnr] whitequark 0d164cc - Update dependencies.
<awygle> you _must_ be able to assign to the result of bit_select/word_select, right?
<awygle> oh i think i see what's up... maybe
<_whitenotifier-f> [nmigen] jfng opened pull request #499: hdl.mem: document ReadPort and WritePort. - https://git.io/JU4Ve
<awygle> okay i'm wrong, i have no idea what's going on
<awygle> https://gist.github.com/awygle/1424949bd2e1c41fba6db2d3871dfe10 can somebody take a look at this and tell me if it _should_ work?
<awygle> should be a pretty minimal example
<awygle> (obviously this can be pretty trivially reworked, so it's not like, a functional problem, just surprised me)
<jfng> .bit_select() returns a Part, .word_select() returns a Slice
<jfng> .bit_select().word_select() returns a Slice whose LHS is a Part, which is apparently not supported by the rtlil backend
<awygle> this also works with double bit_select btw
<awygle> or uh. double bit select also does _not_ work, rather
<awygle> and neither does double word_select
<jfng> uh, i actually don't understand what's going on here, so i'll bail out :p
<d1b2> <Banana Phone> is it possible to platform.request a connector from an array
<jfng> do you mean, in an array ? as in [platform.request("foo", i) for i in ...] ? if so, yes
<d1b2> <Banana Phone> I cant for the life of me figure out how to connect things to pins on my orangecrab
<d1b2> <Banana Phone> in nmigen
<d1b2> <Darius> @Banana Phone platform.request("some_io_name") ?
<d1b2> <Darius> assuming there is a precanned orange crab platform class anyway
<d1b2> <Banana Phone> I'm trying to figure out how to request the things in the connectors array
<d1b2> <Banana Phone> the ones mentioned in lines 80-103
<d1b2> <Darius> can you just do platform.request("0") (or cpio, a4, etc)
<d1b2> <Banana Phone> I dont think so but lemme try
<d1b2> <Banana Phone> nmigen.build.res.ResourceError: Resource 0#0 does not exist
<d1b2> <TiltMeSenpai> yeah
<d1b2> <Darius> hhhh
<jfng> this is not very well documented, sorry about that
<d1b2> <TiltMeSenpai> generally speaking, resources in nmigen should have a purpose, which implies an io standard
<d1b2> <Banana Phone> thank you so much!
<d1b2> <TiltMeSenpai> so you need to platform.add_resource to set the io standard for those pins
<d1b2> <Banana Phone> I really appreciate all the help
<d1b2> <Banana Phone> do I have to import the Resource class somehow?
<jfng> yep, it is in nmigen.build
<d1b2> <Banana Phone> thank you!
<d1b2> <Banana Phone> YAY I DID IT
<jfng> congrats!
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<awygle> nice! :)
<awygle> i know i found an example of Assert-ing a state machine's state
<awygle> somewhere, at some point
<awygle> does anybody know where that was, or have something similar? i remember you had to mess with fragments...
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<awygle> lmao just saw the warnings.warn in nmigen.test.utils
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<d1b2> <Banana Phone> hey I'm a little stuck
<d1b2> <Banana Phone> how do I do inputs with something like buttons
<d1b2> <Banana Phone> I'm trying to make a ripple-carry adder
<d1b2> <Darius> @Banana Phone you need to debounce stuff like buttons BTW
<d1b2> <Darius> you will see multiple edges
<d1b2> <Banana Phone> yeah I saw that. was just gonna hold them down for now
<d1b2> <Banana Phone> I'm trying to individually address an array of input signals
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<d1b2> <Darius> @Banana Phone I mean.. even if you hold it down you will see edges when you push the button, mechanical things are messy 🙂
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<MadHacker> vpn-08911ee6e2d7918a0
<MadHacker> Oops, sorry, mispaste.
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<lkcl__> awygle: suggest comb assigning to a temporary / intermediary the 1st bit_select.
<lkcl__> or compressing it down to 1D by calculating what is actually needed.
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<lkcl__> it's probably this: s.bit_select(i, min(len(s), 16)).eq(d)
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<DaKnig> when I use operator * (to multiply some signals), does it get translated into multiplication in Verilog?
<DaKnig> ... does Verilog even have operator *
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<_whitenotifier-f> [nmigen-boards] whitequark commented on pull request #111: Arty S7 OpenOCD Support - https://git.io/JU4bg
<whitequark> DaKnig: it does, and it does
<whitequark> awygle: if you word-select past the end of a signal it sign-extends the signal on reads, and ignores the high bits on writes
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<whitequark> awygle: re FSM states, you can use fsm.ongoing("STATE") to assert on a specific state, no need to dig out the fragment
<_whitenotifier-f> [yosys] whitequark commented on issue #17: YoWASP yosys fails to generate SVG diagrams - https://git.io/JU4Al
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #499 commit - https://git.io/JU4AB
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #499 commit - https://git.io/JU4AR
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<awygle> whitequa1k: don't you need to dig out the fragment to get at the fsm tho?
<awygle> (also why "ongoing")
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<_whitenotifier-f> [nmigen-boards] benx45h opened pull request #113: Added support for the Cyclone IV de0_nano board - https://git.io/JUBIJ
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<cesar[m]> awygle: you can do: "with m.FSM() as fsm:" to access the fsm. Then, "Assert(fsm.ongoing('state')"
<awygle> hm. but you can only do that within the context manager, right?
<awygle> what if i want to assert the fsm state from outside the context manager, or outside the elaborate method/module entirely?
<cesar[m]> fsm seems to be valid and accessible outside the context manager.
<awygle> ... python...
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<_whitenotifier-f> [nmigen-boards] cr1901 synchronize pull request #111: Arty S7 OpenOCD Support - https://git.io/JUlb0
<agg> awygle: you can save it, like with m.FSM() as fsm: self.fsm = fsm
<agg> or just store the result of fsm.ongoing('state')
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