<DaKnig>
so Memory works the same way as AsyncFIFO, right? you specify the clock domain of the port, then in the comb domain specify the addr (and data in case it's a write port), then one clock later it updates (or reads the value out in read ports)
<DaKnig>
is that correct?
<yuriks>
DaKnig: clock-domain crossing is enough of a chore/footgun that it might still make sense to use an async fifo for it. that neatly prevents you from being tempted to do anything wrong :P
<DaKnig>
ok
<DaKnig>
will do
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* zignig
spends 4 hours chasing a missing line of code.
* zignig
has luna-usb-acm > boneless , RX only.
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<Degi>
Can I nest FSMs?
<Lofty>
Degi: as far as I know, no
<Degi>
Awwh okay
<Lofty>
Since FSMs work by a context manager I'm not sure if nMigen has enough context to distinguish an inner Case from an outer Case
<Lofty>
Easiest way is to just try it though
<Degi>
Hm distinguishing the cases isnt too important, but I need to keep their states separate and only do the inner FSM if the outer FSM is in the right state. But I can implement it using two FSMs and a few signals I think
<Lofty>
You can have multiple FSMs
<Lofty>
Just not nested FSMs
<Degi>
Yes, that's what I will do then
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<DaKnig>
I am confused about how Memory works. I thought you just read and write to the rd/wr ports in the right clock domain and it would detect this to know when to update the internal memory/data port? but it does not look like it works this way
<lkcl>
that's a "wrapped" one that has a port-forwarding "bypass" on it, so that if write comes in on the same cycle as read, the read data is returned from the *write incoming data*, *not* the actual Memory.
<lkcl>
why?
<lkcl>
because reads - and writes - are one cycle *late*.
<lkcl>
for a synchronous Memory, you initiate a read, the response is valid on the output bus *one cycle later*
<DaKnig>
this "self.synched" param determines if the read port is synchronous (data arrives a clock later) or async (data is available immediately) right?
<lkcl>
something like that, yes.
<lkcl>
one of them will be mapped to FPGA BRAM
<lkcl>
the other will not
<DaKnig>
in series 7 FPGAs apparently it might map to distributed RAM for async read ports (this even takes less resources!)
<DaKnig>
sometimes it would also detect sync reads as distributed ram, so it might not be always bram even if it meats all the criteria