ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at · IRC meetings each Monday at 1800 UTC · next meeting September 14th
<d1b2> <Banana Phone> Are there any nmigen vga examples?
<d1b2> <Banana Phone> also could someone explain how clocks work in nmigen
<d1b2> <Banana Phone> sorry for asking all of these basic questions. I'm pretty new to fpgas
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* zignig has a Elaboratable that only works if the Temperature is above 22.5C , considering clock res.
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<zignig> yep, clock is TOO slow.
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<mithro> ktemkin: Where does the "serial USB ACM" example using LUNA live? I'm having trouble finding it in the docs?
<mithro> ktemkin: Searching for acm doesn't seem to turn up anything?
<ktemkin> the examples are all in that folder
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<mithro> ktemkin: Not urgent - :-)
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<awygle> ktemkin: is usb-PD in scope for Luna?
<ktemkin> awygle: gateware? yes; especially once the USB3 work is done
<ktemkin> hardware? not until after I start selling the inexpensive USB2 design and start designing a much-more-expensive-but-USB3-and-friends one
<awygle> I meant gateware in this case. Good to know! Thanks
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<tpw_rules> this may be fixed in a later version but with m.If(blah): with m.Elif(blah2): does not raise a SyntaxError("Elif without preceding If")?
<tpw_rules> well more correctly m.If(blah):\n\twith m.Elif(blah2):
<awygle> huh, indeed it does not, even in my fairly-recent checkout
<awygle> oof i thought this might be an easy fix but the way the context managers are implemented is a bit beyond me
<awygle> at least without spending a bit more time
<tpw_rules> i could file a bug on github if that helps
<awygle> go for it :) then we won't lose track of it (even if wq comes back and says "yeah this is impossible because <complicated python stuff>")
<d1b2> <EmilJ> current status: I want to get nmigen running on my Pynq-Z2, so I am editing nmigen-zynq, which only supports Zynq Ultrascale+ MPSoC to support Zynq 7000 (
<d1b2> <EmilJ> these series have different processing systems including different naming of things, which is frustrating
<_whitenotifier-f> [nmigen] tpwrules opened issue #500: Elif without If not recognized in nested If -
<vup> @EmilJ not sure what you want to do / if this helps you, but anuejn and I have a bunch of zynq 7000 wrapper stuff here:
<tpw_rules> whee i have the 500th problem :D
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<ademski> Hi, I'm trying to instatiate a closed source core as an Instance and i need to propagate diff ref clock (clk_p, clk_n) as port of the top level without any buffer. Is this posible? How can i dissable buffer instatiation for those ports?
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<d1b2> <EmilJ> vup: that looks exactly like what I am doing. Except the way it is done in nmigen-zynq is a big ol' list of strings, naming the primitives, after which they are requested via string. It's kind of awkward and TCLy. Not very snekthonic at all!
<vup> ademski: `dir="-"` when you request it
<ademski> vup: oh, that is easy! thanks!
<d1b2> <EmilJ> what I don't understand in the apertus nmigen gateware project is that I don't see some sort of interface from, for example, EMIO primitives, to the more abstract nmigen IO access - is this wrapper only covering the minimum interfaces needed for the project?
<vup> well
<vup> it uses yosys to dynamically and automatically generate a wrapper for every port of the PS7
<vup> that is why there is no explicit code that mentions EMIO, you can however access it like the axigp / axihp stuff for example
<d1b2> <EmilJ> that's interesting. That's what the yosys JSON parsing utilities do?
<d1b2> <EmilJ> Also I'm surprised that declaring an AXI isn't parametrized to which hardware resource you want, it seems like you'd want to always be working with a specific AXI because you are interfacing with software which expects your module to appear on a specific bus
<d1b2> <EmilJ> (does the IRC bot support edited messages?)
<vup> yep, thats what the yosys json parsing thing is for.
<vup> we have not needed specific AXI port numbers for this yet, the goal is more to automatically generate the software according to the gateware and (dynamically) load that
<vup> for example there is also code that can automatically generate devicetree overlays with the correct address for memory mapped registers
<vup> or code that generates python code to access memory mapped registers by name / hierarchy
<d1b2> <EmilJ> Very cool. I have no idea how devicetree overlays work. The extent of my experience is looking at the zynq datasheet, and loading a LED blinky bitstream (not overlay) from the silly little jupyter notebooks server, which obviously crashed the linux server. But the LED did blink :D
<vup> lol
<d1b2> <EmilJ> How do you get the Zynq to map axi addresses to memory?
<vup> EmilJ there are specific memory regions that get mapped to the axi ports
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<ademski> the axi addresses are described at page 112 of the zynq 7000 trm:
<d1b2> <EmilJ> Yeah, I actually have that open right now
<d1b2> <EmilJ> however I was thinking along the lines of virtual memory
<vup> ah, well we just mmap /dev/mem
<d1b2> <EmilJ> so if I write a userspace program under linux which is to access a programmable logic resource, I would use POSIX calls that map the known static address to
<d1b2> <EmilJ> yep exactly
<d1b2> <edbordin> Irc bot doesn't support edited messages because irc itself doesn't support it (the irc server literally just relays messages as they are sent)
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