ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at · IRC meetings each Monday at 1800 UTC · next meeting September 7th
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<_whitenotifier-f> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1]
<_whitenotifier-f> [YoWASP/yosys] whitequark 159f5f0 - Update dependencies.
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<awygle> re-reading the fst paper
<awygle> for some unknown reason
<awygle> the weirdest thing is how vcd-focused it is
<awygle> the comparisons aren't "a simulation output as multiple formats, one of which is vcd and one of which is fst"
<awygle> it's "we have a 5GB vcd file and we turned it into fst and some proprietary formats"
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<whitequark> awygle: hi!
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to cxxsim [+3/-0/±4]
<_whitenotifier-f> [nmigen/nmigen] whitequark 500a581 - [WIP] sim: add cxxsim engine.
<_whitenotifier-f> [nmigen] whitequark commented on issue #455: cxxsim: synchronous assignment inside If statement is not executed -
<_whitenotifier-f> [nmigen] whitequark closed issue #455: cxxsim: synchronous assignment inside If statement is not executed -
<_whitenotifier-f> [nmigen] whitequark commented on issue #439: fsm_state changes mid cycle -
<lkcl__> we have a successful Litex BIOS boot of LibreSOC core on a Versa ECP5! the DDR3 memtest passes, it was the last remaining blocker
<whitequark> meanwhile i have largely finished cxxsim
<whitequark> four tests from test_sim fail; two because of underspecified behavior, one because of... well, different kind of underspecified behavior that's easier to deal with, and one because of a bug in cxxrtl related to async memory read ports
<lkcl__> whitequark: ah superb. does cesar[m]'s unit test pass?
<whitequark> yeah
<lkcl__> ahh superb
<lkcl__> is everything in the same branch as last time?
<lkcl__> or committed to master
<whitequark> yes, and you also need to upgrade yosys to about one minute ago
<lkcl__> ok :)
<whitequark> yes as in cxxsim branch
<lkcl__> got it
<whitequark> there's a bunch of dirty tricks in the code for now
<whitequark> but nothing that will take a long time to fix
<_whitenotifier-f> [nmigen] whitequark commented on issue #439: fsm_state changes mid cycle -
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<_whitenotifier-f> [nmigen] cestrauss commented on issue #439: fsm_state changes mid cycle -
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<DaKnig> if I attach multiple processes, they all happen "in parallel" right? so if all of them are synchronous, the sim clock would move forwards only once all of them `yield`, is that correct?
<awygle> Morning whitequark
<FL4SHK> DaKnig: what did you decide for HDMI?
<FL4SHK> something about actually generating VGA?
<FL4SHK> I myself haven't yet started using my Arty A7
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* awygle yawns
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<awygle> Sounds like you got things figured out! Awesome :-)
<FL4SHK> awygle: who do you mean?
<FL4SHK> Maybe Da Knig
<awygle> Na, whitequark. Scrollback suggests a cxxsim breakthrough
<d1b2> <EmilJ> morning, americanos. I finished undergrad yesterday, I'm going through some FPGA/HDL literature, going to look deeper into nmigen's implementation, and hopefully will go play with glasgow nmigen in an attempt to end up doing the compat layer rewrite we talked about ~2-3 weeks ago
<awygle> sweet
<awygle> congrats (again, I think?)
<d1b2> <EmilJ> yep lol
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<DaKnig> FL4SHK: gave up.
<FL4SHK> DaKnig: are you using a physical VGA to HDMI converter?
<FL4SHK> I've got two of those
<FL4SHK> I was thinking of using them, but
<FL4SHK> now I kind of want to do HDMI
<FL4SHK> I lack a PMOD thing for HDMI
<DaKnig> I use PMOD VGA thing
<FL4SHK> cheater!
<DaKnig> shutup :)
<DaKnig> if it works... it works
<FL4SHK> Yeah, it was my solution too
<FL4SHK> but my new monitor will necessitate me using a translator from VGA to either... looks like displayport (don't have anything that uses non-mini displayport) or HDMI
<DaKnig> I just got a free monitor from the trash. sorks perfectly fine, but its just old.
<DaKnig> enough for my low res
<FL4SHK> I want to try 1080p VGA
<DaKnig> good luck :_
<DaKnig> :)
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<_whitenotifier-f> [nmigen-boards] peteut opened pull request #109: genesys2: employ ULPI resource. -
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<lkcl__> DaKnig: about those multiple processes: effectively, yes. the "tick" affects (applies to) them all
<lkcl__> however - and this is where you would have to be careful: let's say you have two objects with different clocks (asynchronous, or a PLL)
<lkcl__> in one "process" you yield a tick of e.g. 1e6
<lkcl__> and in the *other* process you yield a tick of e.g. 0.5e6 (twice the rate)
<lkcl__> (because one process is testing the part of the design that runs at 2x the rate of the other process)
<lkcl__> there, naturally/obviously, the two processes are *not* going to be "running at the same rate", are they?
<lkcl__> the reason i mention it is because i remember that you asked about how to set up a PLL for the VGA object
<lkcl__> i would really strongly suggest you get the test/simulation working with one and only one clock, first.
<DaKnig> yeah ik that
<DaKnig> there is a param you pass for that
<DaKnig> to tell it what clock domain it uses mainly
<lkcl__> oh that's interesting, i didn't know that. that's really useful
<DaKnig> that's from the tutorial you sent me :)
<lkcl__> haha i missed it
<DaKnig> I have two processes that communicate with eachother via a global (its fine.) and it looks like each time I run the sim it executes them in a different order
<DaKnig> is it using a set for events? or for the processes? or some other unordered thing?
<DaKnig> in my case it really does not matter.
<DaKnig> I just wanted to point this out.
<lkcl__> using a global to communicate.... (which is fine), however have you created a synchronisation protocol?
<DaKnig> or maybe I have an error somewhere
<lkcl__> some sort of handshaking (req / ack) ?
<DaKnig> one of the processes is just a counter
<DaKnig> just counts the cycles, the other prints it once per uh
<DaKnig> 10k counts
<lkcl__> and they're in the same clock domain, and the counter is updated using "sync"?
<lkcl__> have you examined the vcd trace with gtkwave?
<awygle> oh hooray. pip is broken again.
<DaKnig> hte counter counts up once per `yield` (consistently)
<DaKnig> this is just a global python var, not a signal
<DaKnig> it really does not matter.
<lkcl__> DaKnig: ah ok.
<lkcl__> oh. right. ah: are you outputting debug print statements from two different simulation processes?
<lkcl__> and you're asking, "why is the order sometimes different?"
<lkcl__> are you asking, "why sometimes does one print statement from one process come before another print statement from the other process, even though they are the exact same tick"
<lkcl__> is that right?
<DaKnig> one debug thing was already written, then I realized I want a separate process that would print the counter
<DaKnig> I didnt want to write the same prints everywhere in the big process
<DaKnig> it looks like in some runs the counter is off by one
<DaKnig> which means the print is executed before the counter goes up
<DaKnig> but again, it really does not matter.
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<lkcl__> this will do a byte-wise word select, right?
<lkcl__> kcl__> i mean word_select
<lkcl__> <lkcl__> dsel = data_fwd.word_select(i, 8)
<lkcl__> <lkcl__> comb += data_out.word_select(i, 8).eq(dsel)
<DaKnig> should work, yeah
<lkcl__> cool, thx. each of those has a "with m.If(valid[i])" check before it. it's like wishbone sel.
<DaKnig> what's with the weird messages?
<DaKnig> copied from another place?
<DaKnig> if you are on your computer, and if you are using a terminal-based irc client, you might be able to select a rectangular area instead of lines... in gnome-terminal it's "hold Ctrl and select with the mouse"
<DaKnig> very handy
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<DaKnig> test
<awygle> test?
<DaKnig> ok it works.
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<DaKnig> how can I change the direction of a memory port?
<DaKnig> BRAM in 7-series FPGAs can have only two ports; but I can change the direction of each one in runtime. how would I do this in nmigen?
<DaKnig> (and is this even possible?)
<DaKnig> (without resorting to using primitives
<awygle> don't take this as authoritative but that soundsl ike you'd have to use the primitives as Instances to me
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<DaKnig> :(
<DaKnig> I'd rather avoid this. I guess I would change the design accordingly.
<daveshah> Yeah, I don't think Yosys can represent this in a way that the Verilog output would be correctly inferred by Vivado
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<daveshah> You could try using separate read and write ports with the same address and see if Vivado infers TDP RAM
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<DaKnig> how do I implement a system with a single producer and multiple consumers?
<DaKnig> where all consumers are synchronous and phase-aligned to each other and the producer
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<awygle> you need an arbiter
<DaKnig> ok
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<DaKnig> can I have a specific Record as a datatype?
<DaKnig> for example if I want to represent a Color as a Record, instead of just writing "Record( ....)" each time, just write "Color()"
<DaKnig> I mean a way besides inheritance from Record; that's what I am currently doing (I know its unsupported)
<awygle> you can make a function called Color() that returns your record
<DaKnig> do states in m.FSM accept spaces in state names?
<DaKnig> also, thanks awygle that might help.
<awygle> i believe the state names can have spaces, they're just python strings
<DaKnig> are they propogated into Verilog output?
<awygle> i don't know the answer to that. they are propagated into *vcd* output
<DaKnig> ... looks like verilog does not have enums at all
<DaKnig> SystemVerilog does tho
<awygle> correct
<DaKnig> how does state transition work in m.FSM? is it synchronous? according to what clock domain?
<awygle> you can pass a domain to m.FSM
<awygle> it defaults to 'sync'
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<yehowshuaimmanue> whitequark, I know you were thinking of ways to get rid of Settle?
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<Yehowshua> The main way I use settle is to observe the current value of a signal during a testbench
<Yehowshua> For example, when you do `yield sig`, it returns the values on the left side of the positive clock edge
<DaKnig> are you suggesting to `Settle` at each read?
<DaKnig> that'd be horrible
<DaKnig> imo
<Yehowshua> You could be right
<Yehowshua> What do you see going wrong?
<DaKnig> speed
<Yehowshua> Well, yeah
<DaKnig> it's already slow as is, now adding extra logic to each read would be even slower
<DaKnig> think about what happens when you are reading a frame of VGA
<Yehowshua> hmm
<DaKnig> or worse , a frame of HDMI (that's 10 times the info!)
<DaKnig> (and requires more logic to decode)
<awygle> i misread that as "get rid of seattle" and was briefly concerned
<DaKnig> LOL
<Yehowshua> Well, I was thinking Settle was going to be phased out...
<DaKnig> read again
<DaKnig> :)
<Yehowshua> Getting rid of Seattle would be very bad :P
<Yehowshua> I'm assuming that was a typo on your part
<DaKnig> try to not use very long names, ok? :)