ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting September 14th
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<BracketMaster> whitequark, running cxxsim on commit 9b46ce962c22dce6804a7a61531f04eeff24d6ae
<BracketMaster> on a design on medium complexity, say 1000LUT4s, 10BRAM4Ks
<BracketMaster> pysim: 77s, cxxsim: 78s
<BracketMaster> ^^of medium complexity, not on
<BracketMaster> Anyways, just some numbers for ya
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<tpw_rules> can nmigen memories set read after write (or write after read) behavior or am i just limited to whatever is inferred?
<whitequark> tpw_rules: try transparent=True/False
<whitequark> BracketMaster: yeah, I'm virtually certain that can be improved (for cxxsim that is)
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<tpw_rules> whitequark: setting transparent=True gives a traceback "TypeError: Value (const 1'd1) cannot be used in assignments"
<tpw_rules> i guess elsewhere. what does transparent=True imply for the rest of the interface?
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<whitequark> tpw_rules: it currently hardcodes .en as 1 because of a Yosys limitation :/
<tpw_rules> for which side?
<whitequark> read
<whitequark> would be pretty useless if it was the write side heh
<tpw_rules> yeah i figured. ok so i set en to 1 but it still gives that error. it says it's on the assignment to the data of the write port
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<tpw_rules> oh that happens if i assign anything to the read port en. strange
<whitequark> yes
<whitequark> it's inconvenient, and unfortunately intended at the moment
<whitequark> due to a yosys limitation
<whitequark> sorry :/
<tpw_rules> additionally it seems ISE does not then infer a read first BRAM
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<whitequark> tpw_rules: with transparent=True?
<DaKnig> why is `nmigen/lib/__init__.py` empty?
<whitequark> what should be there instead?
<DaKnig> idk, having an empty file that does nothing seems redundant
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<ronyrus> how is the order of visiting "elaborate()" function determined in nMigen?
<ronyrus> is it, just the order inside submodules recursively?
<whitequark> ronyrus: it's unspecified; if you have to rely on it, something likely went wrong
<whitequark> one of the the reasons __init__ and elaborate() have been separated is to let you put all the order-dependent code that mutates elaboratables into __init__ or accessory methods, where you can control the order
<whitequark> what prompted the question?
<awygle> good morning, everything is on fire
<whitequark> hi awygle
<whitequark> i didn't realize you were in the bay area
<whitequark> holy shit
<awygle> yep
<whitequark> holy *shit*
<awygle> yep
<whitequark> ok that's still a lot of fire
<ronyrus> @whitequark I did something hacky I admit :) I wanted to use some signals from a submodule of a module I instantiate. But because it's elaborate() called after my elaborate() I couldn't expose these signal. Hence the question.
<whitequark> ronyrus: what if you create the submodule in __init__ and assign it to self.<name> ?
<whitequark> then in elaborate() you could do m.submodules += self.<name>
<ronyrus> sounds interesting, I'll try
<awygle> Yeah not the best visualization, but it's the spread more than anything.
<whitequark> ronyrus: code that depends on elaboration order tends to be really fragile with few workarounds when it breaks
<awygle> My partner and I live on either side of the big dark spot in the upper left here https://twitter.com/macronencer/status/1303662254831865857?s=19. Anyway. This is #nmigen lol
<awygle> I didn't realize you could make a Module in __init__, although it makes sense
<whitequark> awygle: you could, though that's not what I'm recommending
<awygle> ah, I misread
<whitequark> the idea is that you can create (some) sub-elaboratables in __init__, so that you can mutate them easily
<whitequark> as a part of some setup code
<whitequark> this comes up in nmigen-soc especially often
<awygle> Yeah I do that a lot, but I always feel like I'm doing something wrong when I do
<whitequark> nope, this is very much explicitly intended
<whitequark> and a feature in nmigen's design
<whitequark> i should mention that in the docs
<awygle> I am surely not telling you anything you don't know but we really need to (figure out and then) document some conventions including but not limited to what goes in __init__ vs elaborate and whether an interface signal should be passed in to the constructor or just a property
<whitequark> yep absolutely
<ronyrus> yeah, that worked. and it's really good to know that ...
<jfng> whitequark: could you have a look at https://github.com/nmigen/nmigen-soc/pull/27 when you get the time ?
<jfng> the proposed changes impacts existing code in subtle ways, so it would benefit a lot from your insight
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<whitequark> jfng: will do soon
<jfng> thanks !
<whitequark> i gave it a quick look already and i think it's fine, i'll take a closer look in a bit but i don't expect issues
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<awygle> lkcl__: your bouncer is flapping, you've been joining and unjoining with some regularity for the last three or so hours
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