ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting September 14th
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<_whitenotifier-f> [nmigen-boards] tdaede opened pull request #114: ulx3s: fix copy-paste error in GPIO mappings. - https://git.io/JUuRd
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<sebinho> Hi Everybody, I just started investigating the use of nmigen for one of our projects. My main question is regarding simulation. How does the simulator compares to Cocotb? I have been using Cocotb extensively and was very pleased with it. Thx for your help
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<sebinho> so basically we have a lot of existing VHDL code that I was simulating with cocotb. Now we are looking into nmigen as a new way to implement new modules. Is there an easy way to use existing VHDL source files together with nmigen and get simulation support?
<ademski> whitquark is developing cxxsim backend which i suppose it is going to enable that. Currently i'm using nmigen-cocotb (https://github.com/andresdemski/nmigen-cocotb). It just support verilog sources but you can use yosys-ghdl pluging to convert sources.
<sebinho> so if I understand correctly, the Yosys plugin would convert my VHDL into an intermediate format that can be used by nmigen for simulation?
<ademski> I'm using the following comand to convert vhdl to verilog: "ghdl --ieee=synopsys --std=08 -fexplicit -O3 --work=work {vhdl_files} -e {toplevel}; write_verilog {output_file}"
<ademski> After that, you can use nmigen-cocotb to simulate your sources.
<sebinho> I see thx for the explanation. How do you guys compare cocotb and nmigen simulator in terms of features? Why would you stick to cocotb instead?
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<sebinho> For those who have VHDL files already, another solution is to use Icarus Verilog to convert the nmigen Verilog files to VHDL. Then you can use cocotb and GHDL to simulate a complete VHDL design. https://iverilog.fandom.com/wiki/Using_VHDL_Code_Generator
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<ademski> I didn't know that, thanks!
<vup> I think daveshah has also used cxxrtl (basically the backend of cxxsim) to simulate verilog together with vhdl, so you don't necessarily have to convert your files
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<ademski> cocot vs nmigen-pysim ... I have a lot of simulation drivers in cocotb, that is why im stick to cocotb.
<sebinho> @vup daveshah indeed I did read something about cxxrtl. In that case I suppose the simulation will be in C++?
<vup> sebinho: if you use cxxrtl directly yes, however cxxsim is a way to use it from python with the same API as the nmigen python simulator (pysim)
<sebinho> vup: is there any example available on how to use cxxsim?
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<vup> not sure, its still in development, you can check out the cxxsim branch of nmigen and then specify `engine="cxxsim"` in the constructor of `Simulator` I think
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<sebinho> yup: thx! I will check it out
<sebinho> vup
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<_whitenotifier-f> [nmigen/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JUubX
<_whitenotifier-f> [nmigen/nmigen-boards] tdaede 434702f - ulx3s: fix copy-paste error in GPIO mappings.
<_whitenotifier-f> [nmigen-boards] whitequark closed pull request #114: ulx3s: fix copy-paste error in GPIO mappings. - https://git.io/JUuRd
<_whitenotifier-f> [nmigen-boards] whitequark commented on pull request #114: ulx3s: fix copy-paste error in GPIO mappings. - https://git.io/JUub1
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<awygle> Whoops I'm seven days late for the meeting I see
<whitequark> same deal today as the previous time: does anyone have any blockers i can resolve?
<awygle> Not me.
<jfng> me neither
<Lofty> Nothing here
<Lofty> I might file some issues as reminders to self (or maybe to others to remind me) about getting more Intel primitives sorted out
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* cr1901_modern was on vacation for the first time in two years. Oops ._.
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