<d1b2>
<marble> How do I add a clock to the ports in a simulation?
<d1b2>
<marble> How do I add a clock to the ports in a simulation?
<DaKnig>
you usually dont access the clock as a signal and instead let nmigen do its magic, with clock domains and all that , for you
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<d1b2>
<marble> I just want the trace to automatically show when using gtkwave
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<BracketMaster>
You might try doing ports=[ClockSignal("domain")]
<BracketMaster>
Not necessarily sure if it'll work, haven't tried it
<whitequark>
it won't, though it probably should
<whitequark>
(as in, this would be a reasonable improvement request)
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<Lofty>
So, something mentioned to me was that VHDL lets you define a `std_ulogic_vector(15 downto 12)` and index it with values 12-15 instead of 0-3
<Lofty>
If you try something similar in nMigen, with `Signal(range(12,16))`, it can't be indexed as 12-15, but with 0-3
<Lofty>
Not sure if this counts as a usability issue, but it might trip people coming from VHDL
<Lofty>
whitequark: ^, if you're around
<Lofty>
Use case given is having a 16-bit address line, but only using the top 4 bits in a module
<Lofty>
Having it addressable from the minimum value of the range makes naming consistent
<Lofty>
As a side note, I realised the nMigen example is wrong because range is not in bits
<Lofty>
And `range(2**12, 2**16)` is basically the same as `unsigned(16)` anyway
<Lofty>
given how range() works I don't actually see too much point in this
<Lofty>
Unless we have a bitrange() shape too :P
<awygle>
is bitrange() a thing in python?
<Lofty>
No, but neither is signed()/unsigned()
<awygle>
point
<DaKnig>
Lofty: Signal(range(12,16)) gives you a signal that can hold all the values in range 12-16. in VHDL vector_type(15 downto 12) means it has bits 15:12 inclusive (of some value probably). its not the same.
<DaKnig>
oops you said that later. sorry.
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<lkcl>
Lofty: a simple way to deal with that is create a subset signal "subset_of_addr_top_bits = Signal(4)"
<lkcl>
then m.d.comb += subset_of_addr_top_bits.eq(addr[-4:])
<DaKnig>
lkcl: in VHDL you would be able to address them as 12:15 though
<DaKnig>
not 0:3
<DaKnig>
completely different
<lkcl>
python's nice: negative ranges start from the (MSB+1). something like that
<DaKnig>
from "one past the end" like all langs should :)
<lkcl>
so range(16)[-4:] is equivalent to VHDL 12:15