<sorear>
Lofty: not sure if you're talking about alpha or ia64 but either way I'd have to look at the manuals
<Lofty>
IA64.
<FL4SHK>
I'm not at all familiar with rocket-chip
<sorear>
in general, nobody loves integer divide
<FL4SHK>
I've noticed
<FL4SHK>
there's not really a good reason for that from what I can tell
<Lofty>
...I got divide and multiply mixed up, I do apologise
<FL4SHK>
I'll be supporting vector integer divides, with AVX does *not* do
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<FL4SHK>
I need to study numerical analysis
<FL4SHK>
I think it'd be feasible to simply do Newton-raphson with fixed point and end up with the correct result
<FL4SHK>
don't know how to find the maximum number of iterations to perform Newton-raphson for?
<FL4SHK>
it sounds like an on-paper math problem, which should be fun
<sorear>
well you can do error bounding easily enough
<sorear>
I'm a little confused about how this works for divides, which have 2 arguments, but given that this is a super common implementation strategy I have some confidence it's possible to meet 754's correct rounding requirement
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<lkcl>
FL4SHK: have a look at the jondawson fpu. it's a FSM, trading "long completion time" for "LUTs needed"
<lkcl>
FL4SHK: we didn't implement NR, however my understanding is that you implement them as a FSM and keep on iterating until the error is below the acceptable threshold.
<lkcl>
that means needing to have internal mantissa large enough to hold the intermediate results so that you _can_ detect that
<lkcl>
then, yes, sorear, the rounding is computed from what's left (the remaining bits that didn't go into the output result)
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<d1b2>
<EmilJ> vup: what's your preferred method of getting your bitstream to the board?
<vup>
@EmilJ: re the FIFO making the timing worse: that is really weird, the encoder is the TMDS encoder so it could be possible this will not produce valid TMDS
<d1b2>
<EmilJ> dangit
<vup>
whatever is the most convenient for getting the bitstream to the board for you, for boards with a zynq + ethernet I use ssh to copy it over and load it using the kernel
<d1b2>
<EmilJ> could you build camera.py and check for oserdes timing?
<d1b2>
<EmilJ> hmm, what kernel functionality provides bistream download
<vup>
if you use the xilinx kernel you can echo the bitstream into "/dev/xdevcfg"
<d1b2>
<EmilJ> Direct firmware load for hdmi_test_PynqZ2.bin failed with error -2 meant to send this
<d1b2>
<EmilJ> interestingly enough, the bit2bin file has the same byte count as the bit file as well as the bin file generated by the build automagically
<vup>
I think you need flip_data=True for bit2bin
<vup>
we should make that the default
<d1b2>
<EmilJ> well, I have been running a modded version of program_bitstream_ssh.py
<d1b2>
<EmilJ> which has flip_data=True
<d1b2>
<EmilJ> py bitstream_name = "{}.bit".format(name) bin_bitstream = bit2bin(build_products.get(bitstream_name), flip_data=True) with open(name + ".raw.bin", "wb") as f: f.write(bin_bitstream)
<vup>
hmm shouldn't it be `hdmi_test_PynqZ2.raw.bin` then?
<vup>
-2 would be no such file or directory
<d1b2>
<EmilJ> I have renamed it, after copying it to /lib/firmware
<vup>
and you are sure `/lib/firmware/hdmi_test_PynqZ2.bin` exists?
<d1b2>
<EmilJ> yes
<d1b2>
<EmilJ> `xilinx@pynq:~$ ls /lib/firmware | grep hdmi hdmi_test_PynqZ2.bin
<d1b2>
<EmilJ> should file hdmi_test_PynqZ2.bin return something more specific than "data"?
<d1b2>
<EmilJ> sudo echo "base.bin" > /sys/class/fpga_manager/fpga0/firmware returns zero, and I see the "Done" LED turn off for ~100ms on the board when I do that
<d1b2>
<EmilJ> so it's not like I can't write to the firmware thingy
<d1b2>
<EmilJ> I'll just do the thing I did last time, where I ran the python thingy
<vup>
don't think file knows about the xilinx bitstream format, atleast with its header stripped
<vup>
so data seems appropriate
<d1b2>
<EmilJ> hey, that didn't crash, neat
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<Degi>
A signal being high for 1 clock cycle is enough to make a FSM transition, right?
<Degi>
Somehow my FSM doesn't do that, despite the signal being 1 for one cycle... When I set it to "1" instead of the signal, it proceeds to the next state, so the FSM itself seems to work
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<Degi>
Actually nevermind, something else is broken.