ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at · IRC meetings each Monday at 1800 UTC · next meeting September 7th
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<Yoshi> yo awgle, you're not on irc client?
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<awygle> ? I am
<DaKnig> we all are
<DaKnig> :)
<BracketMaster> Oh, direct message failed
<BracketMaster> as in, lookup for awgle fails
<awygle> There's a y
<awygle> (unless I'm rudely intercepting messages for awgle, who is some other person)
<DaKnig> there's tab autocompletion in many clients
<DaKnig> useful for nicks
<BracketMaster> oh yeah, I can't type
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<_whitenotifier-f> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1]
<_whitenotifier-f> [YoWASP/yosys] whitequark f4ec2f2 - Update dependencies.
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<ktemkin> oh, nice; I accidentally typo'd " =" as " +=", and the infinite recursion that resulted was gnarly ^^
<ktemkin> * as " +="
<ktemkin> translating oMigen code to nMigen is creating some interesting typos
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<d1b2> <edbordin> bug report: "nMigen should solve the halting problem to provide more concise error message"
<d1b2> <edbordin> (intended as a joke, not a dig at anyone, in case that doesn't come across 😛 )
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<whitequark> awygle: ping
<_whitenotifier-f> [nmigen-boards] whitequark commented on pull request #109: genesys2: employ ULPI resource. -
<DaKnig> can I have a state that has two names?
<DaKnig> in m.FSM
<whitequark> what would the utility be?
<DaKnig> equivalent states; sure that is "redundant" but it's easier to reason about
<DaKnig> ... am I talking nonsense again?
<whitequark> i think i see what you mean
<whitequark> no, it's not supported
<DaKnig> ok
<DaKnig> so what'd be the best way right now (without non stable features) to make a wrapper class around Record? whitequark
<DaKnig> I would want to override the __add__ function I think
<whitequark> poke awygle to finish ValueCastable :p
<DaKnig> :(
<DaKnig> awygle: please save me
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<_whitenotifier-f> [nmigen] whitequark commented on issue #492: How do you make a bounded up-down counter without modulo? -
<awygle> whitequark: waiting on pr review :-P
<whitequark> awygle: wait really? i never realized, sorry
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<awygle> s'ok lol
<whitequark> oh fuck's sake, github didn't send me an email about it *again*
<whitequark> it sometimes just randomly doesn't send one of those "PR synchronized" emails and it drives me nuts
<whitequark> no idea why
<awygle> weird
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #449 commit -
<_whitenotifier-f> [nmigen] whitequark reviewed pull request #449 commit -
<whitequark> it's really best to leave a comment
<awygle> noted for future
<awygle> I think the new thing does work? My test still passes anyway
<whitequark> uh, @abstractmethod prevents instantiating classes without those methods being overridden
<whitequark> are you testing for tat?
<whitequark> *that
<awygle> Oh you mean abstract method
<awygle> I misunderstood
<lkcl> whitequark: got a *really* obscure bug for you :)
<lkcl> calling a function inside an m.Elif which returns a Signal to be tested
<lkcl> nmigen.hdl.dsl.SyntaxError: Elif without preceding If
<whitequark> that doesn't sound like a bug to me
<whitequark> do you have an MCVE?
<lkcl> i'll see if i can repro it in an MCVE
<lkcl> gimme 5
<lkcl> ha! yes i can.
<lkcl> ahh it's because there is a Switch statement inside the function
<whitequark> yeah. don't do that
<lkcl> it's obscure lol
<whitequark> it's not a bug, it's a limitation of the current Module design
<lkcl> ahh
<lkcl> all i need do is pass in the Signal rather than have it created in the function.
<lkcl> argh nope
<lkcl> assign to an external signal then
<whitequark> it has nothing to do with the Signal
<whitequark> the problem is that you're using `m` inside the controlling expression of `m.Elif(...)`
<lkcl> as in: turn the code into m.If(is_insn_priv & ....)
<lkcl> ahh got it
<whitequark> it would be nice if the DSL was composable, but at the moment it isn't, and it's not clear how to make it so
<lkcl> sorted. simply moved that function out of the m.Elif()
<lkcl> it looks so nice to call a function with a proper name, and everything! ah well
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* lkcl is adding external interrupts (you probably guessed)
<lkcl> really exciting, i ran microwatt's hello_world and micropython binaries - unmodified - this morning
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<_whitenotifier-f> [nmigen] awygle synchronize pull request #449: Implement ValueCastable -
<awygle> whitequark: your comment is of course correct, do you want ValueCastable to be an ABC? i think we want to avoid polluting the metaclass so that method should throw NotImplementedError or something
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<whitequark> yep, iirc we discussed it and decided against ABCing
<whitequark> hm, Elaboratable *is* an ABC
<whitequark> that was a mistake I think
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<awygle> k I'll make it throw
<awygle> and put in a test
<awygle> whitequark: lol actually the abstractmethod is superfluous
<awygle> since as_value isn't @lowermethod in the base class
<awygle> if you don't override you get the @lowermethod error in __new__
<whitequark> excellent
<awygle> do we want to just remove as_value from the base class so that we can properly detect the difference between "no override" and "no @lowermethod decorator"?
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<whitequark> sounds good; there's no elaborate() in the Elaboratable base class either
<whitequark> I think it can still appear in the docs in spite of that
<_whitenotifier-f> [nmigen] awygle synchronize pull request #449: Implement ValueCastable -
<_whitenotifier-f> [nmigen] awygle commented on pull request #449: Implement ValueCastable -
<_whitenotifier-f> [nmigen] DaKnig commented on issue #492: How do you make a bounded up-down counter without modulo? -
<DaKnig> whitequark: would be cool to be able to hold the fragment that represents m.If, m.Switch...
<whitequark> hold?
<DaKnig> I mean , assign it to a python uh... name? how was that called technically in python?
<DaKnig> like `a= Signal() + Signal()`
<whitequark> `a` is a Python variable
<DaKnig> `a` is now the fragment that represents the operation
<whitequark> anyway, there's no fragment that corresponds to m.If in isolation
<DaKnig> I can use it however I want
<DaKnig> oh?
<whitequark> a Fragment is a specific nMigen class that doesn't even exist until the Module is elaborated
<whitequark> `a` contains an AST for that expression
<whitequark> but there are no ASTs that represent an If statement alone
<whitequark> because If/Elif/Else lowers to an ast.Switch (which is not generally used directly)
<DaKnig> ok I was confused. I meant AST.
<whitequark> the point of a Module is to hold an FSM and bits of intermediate state that determine how If/Elif/Else is eventually transformed to a Switch
<DaKnig> ah.
<DaKnig> I thought that was simple.
<DaKnig> that's why it's so ... out of place and weird.
<DaKnig> by default, `` in `m.FSM` is "stay in the current state", right?
<whitequark> yeah
<DaKnig> generally speaking, a Memory unit with multiple write ports would be slower than a Memory unit with one write port, right?
<whitequark> a Memory with multiple write ports isn't synthesizable
<whitequark> well, not as BRAM with most (all?) commercial an OSS tools
<whitequark> i'm not sure which tools can synthesize it as FFRAM
<DaKnig> .. crap.
<DaKnig> well I guess I can run the logic at x2 slower clock rate
<DaKnig> I can use write ports and read ports at different clock domains , right?
<whitequark> there is a trick to get multiple write ports
<DaKnig> whitequark: what about the question with different domains?
<DaKnig> thanks for the article! will read
<whitequark> re half rate: this is also a valid technique! Xilinx UltraRAM works that way
<whitequark> well, they run the memory at 2x the logic rate instead, but same idea
<DaKnig> so they have a PLL inside wach BRAM?
<whitequark> i don't know how it's implemented, actually
<yuriks> DaKnig: still working on that queue stuff?
<DaKnig> yuriks: the one with multiple producers?
<yuriks> mhm
<DaKnig> I think I solved it ; kinda.
<awygle> it's probably multi-edged
<awygle> at least that's my guess
<yuriks> just curious about how you end up doing it
<whitequark> DaKnig: re different domains: you can do that as long as you synchronize things somehow
<whitequark> you can add some logic that prevents simultaneous reads and writes
<whitequark> or, you can add a 2FF synchronizer to the read port
<DaKnig> I just have a FIFO where producers write to a temp thing, then in order they get into the fifo.
<whitequark> oh
<whitequark> try an AsyncFIFO then?
<DaKnig> whitequark: I dont care about simultaneous reads and writes tbh.
<whitequark> awygle: yeah that's my guess too
<DaKnig> this never happens.
<awygle> Probably asyncfifo is what you want DaKnig
<yuriks> DaKnig: so each producer has a fifo, then you round-robin feed those into another single fifo for the consumer?
<DaKnig> wait; there are two things I am asked about at the same time.
<awygle> whitequark: this is not a pressure thing just a "you didn't get notified last time" thing - I did submit updates to the value castable pr
<DaKnig> yuriks: turns out (after some prototyping) that in my problem the data is produced very slowly. and is consumed equally slowly. what I decided to do is to have a buffer for all the producers, then round robin write em into a fifo, then round robin read from fifo into the consumers
<DaKnig> ... is that even sensible lol
<DaKnig> I hope so
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<DaKnig> async fifo is a fifo where both sides have different clock domains, is that correct?
<awygle> yes
<awygle> it's the closest thing to a "fire and forget" way to cross clock domains that i'm aware of
<whitequark> awygle: yup, seen it
<whitequark> going to merge soon, i think; there's some docs that aren't clearly worded but i'll just rephrase them myself
<awygle> mk, sounds good
<awygle> like i said just making sure
<awygle> once that goes in i'll rebase and wrap up my "move record to valuecastable" pr
<whitequark> yup, sounds good
<DaKnig> I have now multiple clock domains in the same module; what's the way to pass those around?
<DaKnig> to allow me to connect them correctly from the outside
<whitequark> by default, clock domains are global to the entire design
<DaKnig> well I guess the guide calls them "control domains"; my question stands
<whitequark> you can use them anywhere
<DaKnig> wdym "global to the entire design"?
<whitequark> say you do ` += ClockDomain("foo")`
<whitequark> you can use ` +=` or `ClockSignal("foo")` or anything else that *refers* to `foo` anywhere in the design
<whitequark> as long as the module which *adds* `foo` is somewhere in the hierarchy
<DaKnig> so when a submodule is added, the "parent" adds all the missing clock domains to itself?
<DaKnig> is that correct?
<whitequark> mm, you could describe it that way
<DaKnig> ok then how does it actually work inside?
<whitequark> after elaborating the design, all clock domains are propagated "down" (to submodules), and non-local clock domains are propagated "up" (to parent modules)
<whitequark> (a local clock domain is created as ClockDomain(local=True))
<DaKnig> so technically I could add ` += ClockDomain("foo")` to a higher module and then in a module that is lower just use `` without declaring it?
<whitequark> not just "could"; you have to do that
<whitequark> otherwise it'd be two different domains
<awygle> the convention is to have submodules use sync for everything and then use DomainRenamer to connect them to different clock domains higher up the hierarchy
<DaKnig> awygle: in my case a domain uses two clocks.
<DaKnig> whitequark: ok thanks!
<yuriks> DaKnig: I think that's essentially what I said? unless I misunderstood the buffers (I'm assuming they're local to each producer?)
<yuriks> also are you doing strict round-robin or are you doing a priority thing where you consume/feed to any available one but use the round-robin order as tie breaker? you should probably do that
<DaKnig> I dont care about the order :)
<yuriks> mhm, I just mean, if you're using strictly round-robin then you're wasting a bunch of cycles where you could be pushing or popping something instead
<DaKnig> any examples for async fifo with nmigen?
<awygle> from nmigen.lib.fifo import AsyncFIFO, AsyncFIFOBuffered
<awygle> i don't know of any particular examples for usage
<awygle> at least not in the examples/ directory or anything
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<lkcl> whitequark: that's a fascinating resource on multiple write ports.
<DaKnig> the xor trick is very interesting!
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<awygle> xor best gate, don't @ me
<DaKnig> I agree wholeheartedly
<DaKnig> if somebody can send me code that uses AsyncFIFO in nmigen, I'd really appreciate that.
<anuejn> Maybe we should start collecting out of tree nmigen stream Implementations in the stream issue
<anuejn> So that we can see what people already did and what they like / dislike about it
<vup> sounds reasonable to me
<awygle> not a bad idea yeah
<anuejn> Almost certainly there is a stream in luna too
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<awygle> C should define "stronk" symbols, which override strong symbols in the same way strong symbols override weak ones
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<daveshah> The 6 strengths
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<_whitenotifier-f> [nmigen] BrettRD commented on issue #492: How do you make a bounded up-down counter without modulo? -
<_whitenotifier-f> [nmigen] BrettRD closed issue #492: How do you make a bounded up-down counter without modulo? -
<DaKnig> so basically when the reading side from an AsyncFIFO wants to read, they just read the `AsyncFIFO(...).r_data` and `AsyncFIFO(...).r_en.eq(1)`, right?
<DaKnig> this means one can "peek" without actually reading the value
<awygle> yep
<awygle> r_en is basically "consume this value"
<DaKnig> awygle: looking at the example code you provided, it looks like all the wires are driven in comb; so what clock domain does the AsyncFIFO update on?
<DaKnig> can I specify this in some way?
<vup> DaKnig: you give it a r_domain and a w_domain parameter
<awygle> yeah you pass them in, r_domain and w_domain
<vup> the read side lives in r_domain, the write side in w_domain
<awygle> idk why i don't have that in that example
<DaKnig> isnt it better to specify this explicitly?
<vup> well it defaults to read and write, if those suit your needs its probably fine to not specify them
<DaKnig> defaults to read and write?
<vup> r_domain defaults to "read" and w_domain defaults to "write"
<DaKnig> ah domains with those names... ok
<vup> yes
<yuriks> huh, the way that clock domains have dynamic scope (as opposed to signals which have static scope since you need to pass them into the module) is kinda weird now that I think of it