<BracketMaster>
whitequark, as you mentioned, I noticed AFIFOs eat up one BRAM each
<BracketMaster>
Is there any what to turn this off?
<BracketMaster>
And just use DFFs?
<BracketMaster>
My AFIFOs aren't very deep, but each seem to use a 4kBRAM
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<pepijndevos>
Is there a way to detect if a signal is used or assigned to?
<pepijndevos>
It seems _lhs_signals and _rhs_signals give this info, but relying on private fields is probably not ideal.
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<Lofty>
pepijndevos: what's your use case?
<pepijndevos>
Lofty, My Excel compiler has a default dictionary with signals that represent cells. After compilation I want to find out which cells are inputs/outputs.
<Lofty>
pepijndevos: but nMigen has no concept of inputs/outputs
<pepijndevos>
Sure, but some cells will never be used and some will never be driven
<Lofty>
Correct, but nmigen doesn't know. Or care.
<pepijndevos>
eh... last time I tried to assign to a signal that was already being assigned to it did not exactly end well
<Lofty>
How does an Excel cell end up with multiple formulae within it?
<pepijndevos>
It does not. This is about interfacing it to the outside world
<pepijndevos>
I want to hook it up to a bus in a SoC for example
<hell__>
Excel compiler?
<pepijndevos>
So you need to kinda memory-map cells, and writing to a cell that is driven by something else is not going to end well
<pepijndevos>
hell__, yea, I'm compiling spreadsheets to nmigen
<hell__>
O_o
<Lofty>
But there should be a DAG (or...hopefully a DAG) formed by the inputs to a cell and the outputs of a cell
<Lofty>
In other words: you already have this information
<hell__>
(then again, Intel does something similar with their memory controllers' initialization code)
<sorear>
see also, everyone's instruction decoder
<pepijndevos>
I can *obtain* this information if I explicitly keep track of which cells are used where...
<pepijndevos>
But right now I don't, so I would rather just ask nMigen about it's AST.
<pepijndevos>
Right now my compiler just goes cell by cell, hooking up stuff to signals in the big dictionary.
<pepijndevos>
(creating them if they don't exist)
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<whitequark>
pepijndevos: you currently cannot obtain this information through any public interface
<pepijndevos>
Alright
<pepijndevos>
So either I keep track manually or use a non-public interface.
<whitequark>
ideally former
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<BracketMaster>
Same question from earlier... Is it possible to not use BRAMs when creating AFIFOs?
<pepijndevos>
BracketMaster, I think it's up to whatever you use for synthesis to decide that? In Yosys the bram.txt controls the thresholds of when it'll use a bram or not
<BracketMaster>
Ah, thanks
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<d1b2>
<marble> what's the preferred way to make a top level desing buildable for a platform, but also simulatable?
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<d1b2>
<marble> or how do I influce, what the simulate subcommand does?
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<whitequark>
you can't, at the moment
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<d0nker5>
I'm trying to build resources to map to icebreakers pmods, is Pins(names, ...) supposed to handle multiple pins? It looks like it but I can't get it working.
<vup>
(also shows how to use conn, which can use to refer to a Connector, like you probably want to do if your Resource hangs of one of the pmods)
<d1b2>
<arko> Having learn of the nmigen only a few hours ago, I can't quite wrap my head around how it builds so quickly
<d1b2>
<DX-MON> if I hazard a guess, it's because it's a lightweight DSL, Yosys/Next-PNR are also decently fast.. and WQ is a genius programmer
<d1b2>
<DX-MON> (shortened so I don't ping her)
<d1b2>
<arko> Oh wow
<d1b2>
<arko> Yeah, I think my perception of synth/PNR build times is warped. I've been building/tweaking litex for the past few hours... but I just built the blink.v example for the orangecrab in a few seconds.
<d1b2>
<arko> i never want to go back to vivado again 😛
<d1b2>
<DX-MON> ah, yeah.. well.. part of that is the simplicity of blink.v - very little hardware so even a proprietary toolchain CLI will get that done fast as it's not too hard to place and route
<d1b2>
<DX-MON> vivado is a burning pile of..
<d1b2>
<DX-MON> I much prefered ISE and the platform design studio that came before it..
<d1b2>
<arko> uggg me too
<d1b2>
<TiltMeSenpai> nextpnr and friends have definitely made me question needing massive workstations for fpga dev
<d1b2>
<arko> I mean... I learned FPGA's on ISE, but have had such a bad experience with Vivado that I think it's really just a bad program and not just me being cranky
<d1b2>
<TiltMeSenpai> like do we really need this, or is it just because the only customers you care about don't care about needing a beefier computer
<d1b2>
<DX-MON> but.. I have noticed that Yoysys and Next-PNR are able to leverage core count more effectively than most proprietary tool chains and are generally faster.. perhaps because of less legacy or less carting around an OS-in-a-tool amount of compat crap
<d1b2>
<arko> 🙂
<d1b2>
<DX-MON> the general rule of course being that the fewer layers and less code to run.. the faster it'll run once you're outside the core algorithm you're implementing
<d1b2>
<arko> makes sense
<d1b2>
<DX-MON> from what I can tell, the proprietary tools suffer the same problem photoshop has always suffered as the version major goes up
<d0nker5>
thanks vup! I'll look into that a bit more. Also is there Writeup or something on how you do the IO stuff? The tutorials listed seem to mostly focus on the HDL and Simulation, but in the end I'd like to do stuff on HW.
<d0nker5>
If you don't mind, can you look at this? https://pastebin.com/Scv3k5Dm its what I'm currently looking at, I took some of the Icebreaker resources as reference, basically I can control single pins like clk or msb, but I'd like to be able to assign stuff with 7 bit Signals the data stuff does not work.
<d0nker5>
I think I might found a bug -.- always the same... as soon as you invite others.
<d0nker5>
Ok so I understood it correctly the first time around, I'm just a doofus that assigned to the wrong pmod port.
<d0nker5>
Anyways I had another question. How do I synchronize a pin to the clock domain of a Module, In my case I'm currently toggeling a pin, which is halving the clock domains clock, I actually would like to directly have the clock on the clk pin.
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<d1b2>
<TiltMeSenpai> m.d.comb += pin.eq(ClockSignal()) or something I think